diff options
| author | Marshall Buschman <mbuschman@lucidmachines.com> | 2011-06-04 15:45:12 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2011-06-04 15:45:12 +0000 |
| commit | 552ad9f75ed6b72decdfa8768ed2e9753eb5b7fa (patch) | |
| tree | 081df08613c200a19134681b0c78891d47ae897d | |
| parent | fd460e620e8ea945548121d860e032cca9d452bf (diff) | |
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7f0b9df278..41f9a6b86a 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); + // early enable of PrefetchEnSPIFromHost + if (boot_cpu()) + { + __outdword (0xcf8, 0x8000a3b8); + __outdword (0xcfc, __indword (0xcfc) | 1 << 24); + } + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { |