diff options
| author | Keith Hui <buurin@gmail.com> | 2024-05-31 22:40:22 -0400 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-07 22:35:02 +0000 |
| commit | 51a01bdcd65370c29342f51a29fa5741447f09dc (patch) | |
| tree | e7a5c29d230f6d737ffed9dab023681c20b543d2 | |
| parent | 943b540914754004fefa19859bf6526b1c667515 (diff) | |
sb/intel/bd82x6x/early_usb.c: Align native current map with MRC
Replace 3 unused values in the map with those found during a Ghidra
examination of MRC binary, and on hardwares running vendor firmware
(asus/p8z77-m and HP Z210 CMT Workstation).
The outgoing values were introduced in commit 216ad2170ca8
("sb/intel/bd82x6x: Add new USB currents") in anticipation for
Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually
abandoned. Since commit xxxxxxxxxxxx, such values can be placed
directly in the port config, so there should be no hurdle should that
effort be resurrected.
Add a few #defines in pch.h to place some inline documentation
on MRC values, but more will be documented in the future when this
mapping is introduced MRC-side.
Finally, update autoport to match.
Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 13 | ||||
| -rw-r--r-- | util/autoport/bd82x6x.go | 4 |
3 files changed, 18 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 6667d4742b..6c21cf7fe2 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -20,8 +20,9 @@ void early_usb_init(const struct southbridge_usb_port *portmap) * See below. */ const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, - USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353, - 0x20000253, 0x20000053, 0x2000055f, 0x20000f5f}; + USBIR_TXRX_GAIN_DESKTOP6_LOW, USBIR_TXRX_GAIN_DESKTOP6_HIGH, + USBIR_TXRX_GAIN_DESKTOP7_LOW, USBIR_TXRX_GAIN_DESKTOP7_MED, + 0x20000053, 0x2000055f, 0x20000f5f}; int i; /* Unlock registers. */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 040b477d35..f2f02b3eab 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -390,10 +390,23 @@ void early_usb_init(const struct southbridge_usb_port *portmap); /* Up to 14" onboard trace length, up to 8" on wires */ #define USBIR_TXRX_GAIN_DEFAULT 0x20000f57 +#define USBIR_TXRX_GAIN_MOBILE_HIGH USBIR_TXRX_GAIN_DEFAULT /* Up to 10" onboard trace length, up to 15" on wires */ #define USBIR_TXRX_GAIN_HIGH 0x2000055B +/* Desktop 6-series PCHs */ +/* In order: up to and not including 8"/13"/15" on wires */ +#define USBIR_TXRX_GAIN_DESKTOP6_LOW USBIR_TXRX_GAIN_DESKTOP_LOW +#define USBIR_TXRX_GAIN_DESKTOP6_MED USBIR_TXRX_GAIN_DEFAULT +#define USBIR_TXRX_GAIN_DESKTOP6_HIGH 0x20000f5b + +/* Desktop 7-series PCHs */ +/* In order: up to and not including 8"/10"/15" on wires */ +#define USBIR_TXRX_GAIN_DESKTOP7_LOW USBIR_TXRX_GAIN_DEFAULT +#define USBIR_TXRX_GAIN_DESKTOP7_MED 0x20000553 +#define USBIR_TXRX_GAIN_DESKTOP7_HIGH USBIR_TXRX_GAIN_HIGH + /* Miscellaneous Control Register */ #define MISCCTL 0x3590 /* 32bit */ /* USB Port Disable Override */ diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 76411e72a1..e2dc827f1d 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -311,8 +311,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { 0x2000094a: 4, 0x2000035f: 5, 0x20000f53: 6, - 0x20000357: 7, - 0x20000353: 8, + 0x20000f5b: 7, + 0x20000553: 9, } for port := uint(0); port < 14; port++ { |