diff options
| author | Kangheui Won <khwon@chromium.org> | 2022-01-25 17:56:43 +1100 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-01 22:31:56 +0000 |
| commit | 506ca3ef4e78d3b32cddfe81eeaa10af86fd57b6 (patch) | |
| tree | 7b71c44aee5c8dcbc2cdf85a3cba363db4367c46 | |
| parent | 894f6f8229a7bb479c523ce4bcbf927f2d1f1d5b (diff) | |
psp_verstage: add new svc for cezanne
Add svc_set_platform_bootmode svc to cezanne. PSP will use this
information to select proper widevine keybox.
BUG=b:211058864
TEST=build guybrush
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/soc/amd/cezanne/psp_verstage/svc.c | 7 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h | 22 |
2 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index e04c702518..78f71260a4 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -133,3 +133,10 @@ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval); return retval; } + +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); + return retval; +} diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 06e9defea7..ff2144d159 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -50,6 +50,7 @@ #define SVC_READ_TIMER_VAL 0x68 #define SVC_SHA 0x69 #define SVC_CCP_DMA 0x6A +#define SVC_SET_PLATFORM_BOOT_MODE 0x6C struct mod_exp_params { char *pExponent; // Exponent address @@ -136,6 +137,19 @@ struct sha_generic_data { }; /* + * This is state that PSP manages internally. + * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_PRODUCTION in verstage. + */ +enum chrome_platform_boot_mode +{ + NON_CHROME_BOOK_BOOT_MODE = 0x0, + CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, + CHROME_BOOK_BOOT_MODE_PRODUCTION = 0x2, + CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, + CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check +}; + +/* * Exit to the main Boot Loader. This does not return back to user application. * * Parameters: @@ -313,6 +327,14 @@ uint32_t svc_modexp(struct mod_exp_params *mod_exp_param); */ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size); +/* + * Get the Platform boot mode from verstage. Production or developer + * + * Parameters: + * - boot mode + -----------------------------------------------------------------------------*/ +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode); + /* C entry point for the Bootloader Userspace Application */ void Main(void); |