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| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-12 13:54:37 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-23 16:05:06 +0000 |
| commit | 4d192820cd22b019b916cbaab16f0384c661038d (patch) | |
| tree | fea02ac8c8a504dccde4bc5ac45858b9766a369b | |
| parent | 30791639f88b2256000bb03733c3cbab7677795b (diff) | |
nb/intel/sandybridge: Add comment to TC_RWP write
Change-Id: I164daa59696f2fe8de3a4b3e7da46c7c723778eb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9b364ab92b..a21caeacff 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1885,6 +1885,10 @@ int write_training(ramctr_timing *ctrl) int channel, slotrank; int err; + /* + * Set the DEC_WRD bit, required for the write flyby algorithm. + * Needs to be done before starting the write training procedure. + */ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |