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authorFelix Held <felix-coreboot@felixheld.de>2023-11-16 14:03:09 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-11-18 15:37:50 +0000
commit4c4d1948efd39afd2d15cc5efb86cc669cb155a3 (patch)
treeada5205e1aafe75df33c5c97ece66bf4f8333908
parentc8dc4a3bd1f93a02c47768f4ef122f67bb1a8fe3 (diff)
nb/intel/sandybridge: assign host bridge ops in chipset devicetree
Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
-rw-r--r--src/northbridge/intel/sandybridge/chipset.cb2
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c14
2 files changed, 2 insertions, 14 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index 5635ca601e..9fb1701076 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -10,7 +10,7 @@ chip northbridge/intel/sandybridge
end
device domain 0 on
ops sandybridge_pci_domain_ops
- device pci 00.0 alias host_bridge on end # host bridge
+ device pci 00.0 alias host_bridge on ops sandybridge_host_bridge_ops end
device pci 01.0 alias peg10 off end # PEG10
device pci 01.1 alias peg11 off end # PEG11
device pci 01.2 alias peg12 off end # PEG12
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 9511cc323d..6b8971081a 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -390,7 +390,7 @@ static void mc_gen_ssdt(const struct device *dev)
set_above_4g_pci(dev);
}
-static struct device_operations mc_ops = {
+struct device_operations sandybridge_host_bridge_ops = {
.read_resources = mc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
@@ -399,18 +399,6 @@ static struct device_operations mc_ops = {
.acpi_fill_ssdt = mc_gen_ssdt,
};
-static const unsigned short pci_device_ids[] = {
- 0x0100, 0x0104, 0x0108, /* Sandy Bridge */
- 0x0150, 0x0154, 0x0158, /* Ivy Bridge */
- 0
-};
-
-static const struct pci_driver mc_driver __pci_driver = {
- .ops = &mc_ops,
- .vendor = PCI_VID_INTEL,
- .devices = pci_device_ids,
-};
-
struct device_operations sandybridge_cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,