diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-07-16 09:51:03 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-17 22:02:37 +0000 |
| commit | 4c15211a782936485203e858da7bf8cea92fce08 (patch) | |
| tree | a62e26723cab9874658a7e8583ea4a1713693d92 | |
| parent | 7d89264cdf7944004165ad79cb439803a73f4b49 (diff) | |
sb/amd/pi: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I90278683bc22d87364453f316c05afe4cd96b383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/fchec.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/reset.c | 6 |
5 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 6313be7370..59ddbd2cbd 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -17,7 +17,7 @@ const char *intr_types[] = { [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", [0x62] = "GPIO\t", - [0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t", + [0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t", #endif }; diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 95c6d356c1..5e3f7601cd 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -187,7 +187,7 @@ void hudson_clk_output_48Mhz(void) ctrl = misc_read32(FCH_MISC_REG40); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - ctrl &= (u32)~(1<<2); + ctrl &= (u32)~(1 << 2); misc_write32(FCH_MISC_REG40, ctrl); } @@ -198,7 +198,7 @@ static uintptr_t hudson_spibase(void) u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xfffffff0; - if (!base){ + if (!base) { base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base | SPI_ROM_ENABLE); diff --git a/src/southbridge/amd/pi/hudson/fchec.h b/src/southbridge/amd/pi/hudson/fchec.h index 960cd88c23..09abe0e8d0 100644 --- a/src/southbridge/amd/pi/hudson/fchec.h +++ b/src/southbridge/amd/pi/hudson/fchec.h @@ -8,7 +8,7 @@ #include <AGESA.h> #include "FchCommonCfg.h" -extern VOID FchECfancontrolservice (IN VOID *FchDataPtr); +extern VOID FchECfancontrolservice(IN VOID *FchDataPtr); void agesawrapper_fchecfancontrolservice(void); #endif diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 9febc16f7b..ccca1138e7 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -69,10 +69,10 @@ static void lpc_init(struct device *dev) cmos_init(0); /* Initialize i8259 pic */ - setup_i8259 (); + setup_i8259(); /* Initialize i8254 timers */ - setup_i8254 (); + setup_i8254(); /* Set up SERIRQ, enable continuous mode */ byte = (BIT(4) | BIT(7)); @@ -255,7 +255,7 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev) default: rsize = 0; /* try AGESA allocated region in region 0 */ - if ((var_num > 0) && ((base >=reg_var[0]) && + if ((var_num > 0) && ((base >= reg_var[0]) && ((base + res->size) <= (reg_var[0] + reg_size[0])))) rsize = reg_size[0]; } diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index 48751a4e64..fbb62c88fc 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -8,9 +8,9 @@ #include <reset.h> #define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) void cf9_reset_prepare(void) { |