diff options
| author | Xin Ji <xji@analogixsemi.com> | 2021-09-03 11:11:44 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-09-13 06:59:20 +0000 |
| commit | 48ae111ca80e5d35e2fa25fe39cf01bb2fc6e087 (patch) | |
| tree | c21a8ba680a9e978292b1f8bc9ca57466fb91e33 | |
| parent | 3d469fad97f962abb61b5a70837ef96b2c4a78cb (diff) | |
drivers/analogix/anx7625: prevent video clock jitter on IVO panels
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz),
anx7625 defines K ratio for matching MIPI input video clock and
DP output video clock. A bigger k value can match a bigger video data
variation. IVO panel has smaller variation than DP CTS spec, so decrease
k value to 0x3b.
BUG=b:194659777
BRANCH=none
TEST=Display is normal on Asurada
Change-Id: If3a09811999babda45e9a9a559dd447920109204
Signed-off-by: Xin Ji <xji@analogixsemi.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
| -rw-r--r-- | src/drivers/analogix/anx7625/anx7625.c | 16 | ||||
| -rw-r--r-- | src/drivers/analogix/anx7625/anx7625.h | 1 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index e37e047bbd..11e9ed1796 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -381,7 +381,7 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, (n & 0xff)); /* diff */ - ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, dt->k_val); ret |= anx7625_odfc_config(bus, post_divider - 1); @@ -804,6 +804,20 @@ static void anx7625_parse_edid(const struct edid *edid, dt->vback_porch = (edid->mode.vbl - edid->mode.vso - edid->mode.vspw - edid->mode.vborder); + /* + * The k_val is a ratio to match MIPI input and DP output video clocks. + * Most panels can follow the default value (0x3d). + * IVO panels have smaller variation than DP CTS spec and need smaller + * k_val (0x3b). + */ + if (!strncmp(edid->manufacturer_name, "IVO", 3)) { + dt->k_val = 0x3b; + ANXINFO("detected IVO panel, use k value 0x3b\n"); + } else { + dt->k_val = 0x3d; + ANXINFO("set default k value to 0x3d for panel\n"); + } + ANXINFO("pixelclock(%d).\n" " hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n" " vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h index c0b33b2eea..bba42cb61a 100644 --- a/src/drivers/analogix/anx7625/anx7625.h +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -350,6 +350,7 @@ struct display_timing { unsigned int vfront_porch; unsigned int vback_porch; unsigned int vsync_len; + unsigned int k_val; }; int anx7625_dp_start(uint8_t bus, const struct edid *edid); |