diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-04-02 10:16:54 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-04-05 00:44:43 +0000 |
| commit | 4774012515db737c3aada7ced093851346aece4d (patch) | |
| tree | a1a5b1ea2386f6dd5bff74e3c2f9274d495c2735 | |
| parent | f3314c20dede95a50d9c2ba2806c09b7f8728f03 (diff) | |
soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN
This matches the other register definitions.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 152cdd9001..45fcc6f416 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -337,7 +337,7 @@ enum espi_cmd_type { #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) #define ESPI_SUB_DECODE_EN (1 << 2) -#define SLAVE0_INT_STS 0x70 +#define ESPI_SLAVE0_INT_STS 0x70 #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) #define ESPI_STATUS_FATAL_ERROR (1 << 5) @@ -418,9 +418,9 @@ static int espi_wait_ready(void) /* Clear interrupt status register */ static void espi_clear_status(void) { - uint32_t status = espi_read32(SLAVE0_INT_STS); + uint32_t status = espi_read32(ESPI_SLAVE0_INT_STS); if (status) - espi_write32(SLAVE0_INT_STS, status); + espi_write32(ESPI_SLAVE0_INT_STS, status); } /* @@ -433,7 +433,7 @@ static int espi_poll_status(uint32_t *status) stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); do { - *status = espi_read32(SLAVE0_INT_STS); + *status = espi_read32(ESPI_SLAVE0_INT_STS); if (*status) return 0; } while (!stopwatch_expired(&sw)); |