soc/qualcomm: Remove blank lines before '}' and after '{'

Change-Id: If2c2138ed3dc437b924297330805caa8c357853d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

14 files changed, 0 insertions, 30 deletions

diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c
index 9825508c66..65c294097e 100644
--- a/src/soc/qualcomm/common/pcie_common.c
+++ b/src/soc/qualcomm/common/pcie_common.c
@@ -468,5 +468,4 @@ void qcom_setup_pcie_host(struct device *dev)
 		printk(BIOS_NOTICE, "PCIe enumerated succussfully..\n");
 	else
 		printk(BIOS_EMERG, "Failed to enable PCIe\n");
-
 }
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 56fd3bf6a1..97b6e2d4f7 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -124,10 +124,8 @@ static void write_qclib_log_to_cbmemc(struct qclib_cb_if_table_entry *te)
 
 static void write_table_entry(struct qclib_cb_if_table_entry *te)
 {
-
 	if (!strncmp(QCLIB_TE_DDR_INFORMATION, te->name,
 			sizeof(te->name))) {
-
 		write_ddr_information(te);
 
 	} else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name,
@@ -137,13 +135,11 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te)
 
 	} else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name,
 			sizeof(te->name))) {
-
 		assert(fmap_overwrite_area(QCLIB_FR_LIMITS_CFG_DATA,
 			(const void *)te->blob_address, te->size));
 
 	} else if (!strncmp(QCLIB_TE_QCLIB_LOG_BUFFER, te->name,
 			sizeof(te->name))) {
-
 		write_qclib_log_to_cbmemc(te);
 
 	} else if (!strncmp(QCLIB_TE_MEM_CHIP_INFO, te->name,
@@ -151,11 +147,9 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te)
 		write_mem_chip_information(te);
 
 	} else {
-
 		printk(BIOS_WARNING, "%s write not implemented\n", te->name);
 		printk(BIOS_WARNING, "  blob_address[%llx]..size[%x]\n",
 			te->blob_address, te->size);
-
 	}
 }
 
diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c
index ef19053692..14b37daa38 100644
--- a/src/soc/qualcomm/ipq40xx/blobs_init.c
+++ b/src/soc/qualcomm/ipq40xx/blobs_init.c
@@ -113,5 +113,4 @@ void start_tzbsp(void)
 	printk(BIOS_INFO, "Starting TZBSP\n");
 
 	tz_init_wrapper(0, 0, tzbsp);
-
 }
diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c
index 88e9169ec7..9627cbe625 100644
--- a/src/soc/qualcomm/ipq40xx/qup.c
+++ b/src/soc/qualcomm/ipq40xx/qup.c
@@ -199,7 +199,6 @@ static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
 
 	stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
 	while (data_len) {
-
 		tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
 						data_ptr[idx]);
 		data_len--;
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index ab8f53016f..cf5c214f32 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -74,10 +74,8 @@ static int check_bit_state(void *reg_addr, int mask,
  */
 static int check_qup_state_valid(struct ipq_spi_slave *ds)
 {
-
 	return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK,
 				QUP_STATE_VALID, 1);
-
 }
 
 /*
@@ -297,7 +295,6 @@ static void write_force_cs(const struct spi_slave *slave, int assert)
 	else
 		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
-
 }
 
 /*
@@ -354,7 +351,6 @@ static int check_fifo_status(void *reg_addr)
 static void enable_io_config(struct ipq_spi_slave *ds,
 				uint32_t write_cnt, uint32_t read_cnt)
 {
-
 	if (write_cnt) {
 		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
@@ -370,7 +366,6 @@ static void enable_io_config(struct ipq_spi_slave *ds,
 		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 	}
-
 }
 
 /*
@@ -486,7 +481,6 @@ static int __blsp_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer,
 	 * to get the actual data on the subsequent read cycle that happens
 	 */
 	while (write_len || read_len) {
-
 		ret = check_fifo_status(ds->regs->qup_operational);
 		if (ret != SUCCESS)
 			goto out;
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c
index c538c279e8..dd478c4020 100644
--- a/src/soc/qualcomm/ipq806x/spi.c
+++ b/src/soc/qualcomm/ipq806x/spi.c
@@ -161,10 +161,8 @@ static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay
  */
 static int check_qup_state_valid(struct ipq_spi_slave *ds)
 {
-
 	return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_BIT,
 				QUP_STATE_VALID, 1);
-
 }
 
 /*
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index ce846543dc..a3a41c739b 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -144,7 +144,6 @@ static bool clock_is_off(void *cbcr_addr)
 static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
 				uint32_t vote_bit)
 {
-
 	/* Set clock vote bit */
 	setbits32(vote_addr, BIT(vote_bit));
 
@@ -156,7 +155,6 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
 
 static int clock_enable(void *cbcr_addr)
 {
-
 	/* Set clock enable bit */
 	setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 
@@ -169,7 +167,6 @@ static int clock_enable(void *cbcr_addr)
 
 static int clock_disable(void *cbcr_addr)
 {
-
 	/* Set clock enable bit */
 	clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 	return 0;
@@ -303,7 +300,6 @@ void clock_disable_spi(int blsp, int qup)
 		clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
 	else
 		printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
-
 }
 
 void clock_enable_i2c(void)
diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c
index e3a4e5e69e..b5805b046e 100644
--- a/src/soc/qualcomm/qcs405/qup.c
+++ b/src/soc/qualcomm/qcs405/qup.c
@@ -235,7 +235,6 @@ static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
 
 	stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
 	while (data_len) {
-
 		tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
 						data_ptr[idx]);
 		data_len--;
diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c
index 18bf698d5a..c53cbf2b84 100644
--- a/src/soc/qualcomm/qcs405/soc.c
+++ b/src/soc/qualcomm/qcs405/soc.c
@@ -13,7 +13,6 @@ static void soc_read_resources(struct device *dev)
 
 static void soc_init(struct device *dev)
 {
-
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c
index 48631884c7..b263d2fae9 100644
--- a/src/soc/qualcomm/qcs405/spi.c
+++ b/src/soc/qualcomm/qcs405/spi.c
@@ -403,7 +403,6 @@ static int check_fifo_status(void *reg_addr)
 static void enable_io_config(struct qcs_spi_slave *ds,
 				uint32_t write_cnt, uint32_t read_cnt)
 {
-
 	if (write_cnt) {
 		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c
index a43470d612..7f26a68ddd 100644
--- a/src/soc/qualcomm/sc7180/display/dsi_phy.c
+++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c
@@ -483,7 +483,6 @@ static void dsi_phy_pll_bias_enable(bool enable)
 
 	/* pll system muxes */
 	write32(&phy_pll_qlink->pll_system_muxes, reg_val);
-
 }
 
 static void dsi_phy_mnd_divider(struct dsi_phy_configtype *phy_cfg)
@@ -598,7 +597,6 @@ static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg
 
 		/* VCO output freq*/
 		vco_freq_hz = pll_output_freq_hz * pll_post_div;
-
 	}
 
 	return (unsigned long)vco_freq_hz;
diff --git a/src/soc/qualcomm/sc7280/display/disp.c b/src/soc/qualcomm/sc7280/display/disp.c
index fd3ed3ced1..bd2259e01b 100644
--- a/src/soc/qualcomm/sc7280/display/disp.c
+++ b/src/soc/qualcomm/sc7280/display/disp.c
@@ -58,5 +58,4 @@ void mdss_ctrl_config(void)
 
 	/* PPB0 to INTF1 */
 	write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_5);
-
 }
diff --git a/src/soc/qualcomm/sc7280/display/edp_ctrl.c b/src/soc/qualcomm/sc7280/display/edp_ctrl.c
index 469e1b6286..2bf7958293 100644
--- a/src/soc/qualcomm/sc7280/display/edp_ctrl.c
+++ b/src/soc/qualcomm/sc7280/display/edp_ctrl.c
@@ -762,7 +762,6 @@ static bool edp_clock_recovery_reduced_lanes(
 
 static int edp_link_lane_down_shift(struct edp_ctrl *ctrl, uint8_t *dpcd)
 {
-
 	if (ctrl->lane_cnt <= 1)
 		return -1;
 
@@ -1275,7 +1274,6 @@ static void edp_ctrl_timing_cfg(struct edid *edid)
 	write32(&edp_lclk->active_hor_ver,
 		(edid->mode.ha) |
 		((edid->mode.va << 16) & 0xffff0000));
-
 }
 
 static void edp_mainlink_ctrl(int enable)
diff --git a/src/soc/qualcomm/sc7280/socinfo.c b/src/soc/qualcomm/sc7280/socinfo.c
index 80462373fb..af6901eab0 100644
--- a/src/soc/qualcomm/sc7280/socinfo.c
+++ b/src/soc/qualcomm/sc7280/socinfo.c
@@ -80,5 +80,4 @@ uint16_t socinfo_pro_part(void)
 		return chipinfolut[ret].pro;
 
 	die("could not match jtagid\n");
-
 }