diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-17 02:51:11 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-18 14:06:10 +0000 |
| commit | 4235fb6015b7f1ac78b21209cf2ff32b8eb27458 (patch) | |
| tree | 5f5147ff7cb4d213e907571506baa0e2d504a4f1 | |
| parent | 192945e61cef3f90b0a7464b98801b4bd0150ff7 (diff) | |
soc/amd/glinda/agesa_acpi: use acpi_align_current to align IVRS & ALIB
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I965791fbbe499702e191dcbf1f5fbfcb5e1bab6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
| -rw-r--r-- | src/soc/amd/glinda/agesa_acpi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/glinda/agesa_acpi.c b/src/soc/amd/glinda/agesa_acpi.c index 78c0e4cdf3..ae4f10284f 100644 --- a/src/soc/amd/glinda/agesa_acpi.c +++ b/src/soc/amd/glinda/agesa_acpi.c @@ -15,10 +15,11 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current acpi_ivrs_t *ivrs; /* add ALIB SSDT from HOB */ + current = acpi_align_current(current); current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = ALIGN(current, 8); + current = acpi_align_current(current); ivrs = (acpi_ivrs_t *)current; acpi_create_ivrs(ivrs, acpi_fill_ivrs); current += ivrs->header.length; |