soc/intel/xeon_sp: Add ACPI names

Set the unused 'name' property of the domain device and store
the ACPI name. Every IIO stack can have multiple domain devices,
each owning a subset of the available bus range within the stack.

The name will be used in future changes to generate ACPI names
in SSDT code generation. It can also be used to identify the domain
type by looking at the first two characters of the name.

Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80792
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

8 files changed, 85 insertions, 39 deletions

diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index 5eaa76253a..0cc0931e7d 100644
--- a/src/soc/intel/xeon_sp/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <assert.h>
+#include <commonlib/stdlib.h>
 #include <intelblocks/acpi.h>
+#include <soc/chip_common.h>
 #include <soc/pci_devs.h>
 #include <soc/util.h>
 #include <stdint.h>
@@ -125,3 +127,32 @@ size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
 
 	return index;
 }
+
+void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
+{
+	const union xeon_domain_path dn = {
+		.domain_path = dev->path.domain.domain
+	};
+
+	assert(dn.socket < CONFIG_MAX_SOCKET);
+	assert(dn.stack < 16);
+	assert(prefix != NULL && strlen(prefix) == 2);
+
+	if (dn.socket >= CONFIG_MAX_SOCKET || dn.stack >= 16 ||
+	    !prefix || strlen(prefix) != 2)
+		return;
+
+	char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
+	snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%1X%1X", prefix, dn.socket, dn.stack);
+	dev->name = name;
+}
+
+const char *soc_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return dev->name;
+
+	/* FIXME: Add SoC specific device names here */
+
+	return NULL;
+}
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c
index 0c1d52bc86..03ae70af35 100644
--- a/src/soc/intel/xeon_sp/chip_common.c
+++ b/src/soc/intel/xeon_sp/chip_common.c
@@ -2,8 +2,10 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <post.h>
 #include <device/pci.h>
+#include <intelblocks/acpi.h>
+#include <post.h>
+#include <soc/acpi.h>
 #include <soc/chip_common.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
@@ -170,6 +172,9 @@ static struct device_operations iio_pcie_domain_ops = {
 	.read_resources = iio_pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,
 	.scan_bus = iio_pci_domain_scan_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name        = soc_acpi_name,
+#endif
 };
 
 /*
@@ -180,6 +185,9 @@ static struct device_operations ubox_pcie_domain_ops = {
 	.read_resources = noop_read_resources,
 	.set_resources = noop_set_resources,
 	.scan_bus = pci_host_bridge_scan_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name        = soc_acpi_name,
+#endif
 };
 
 /*
@@ -194,6 +202,8 @@ static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus
 		.domain_path = dp.domain_path
 	};
 
+	/* Only expect 2 UBOX buses here */
+	assert(bus_base + 1 == bus_limit);
 	for (int i = bus_base; i <= bus_limit; i++) {
 		new_path.bus = i;
 
@@ -208,6 +218,8 @@ static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus
 			die("%s: out of memory.\n", __func__);
 
 		domain->ops = &ubox_pcie_domain_ops;
+		const char *prefix = (i == bus_base) ? DOMAIN_TYPE_UBX0 : DOMAIN_TYPE_UBX1;
+		iio_domain_set_acpi_name(domain, prefix);
 
 		struct bus *const bus = alloc_bus(domain);
 		bus->secondary = i;
@@ -226,9 +238,10 @@ void attach_iio_stacks(struct device *dev)
 
 	for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
 		for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
-			if (s == 0 && x == 0)
+			if (s == 0 && x == 0) {
+				iio_domain_set_acpi_name(dev, DOMAIN_TYPE_PCIE);
 				continue;
-
+			}
 			const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
 			if (ri->BusBase > ri->BusLimit)
 				continue;
@@ -249,6 +262,7 @@ void attach_iio_stacks(struct device *dev)
 					die("%s: out of memory.\n", __func__);
 
 				iio_domain->ops = &iio_pcie_domain_ops;
+				iio_domain_set_acpi_name(iio_domain, DOMAIN_TYPE_PCIE);
 			} else if (CONFIG(HAVE_IOAT_DOMAINS))
 				soc_create_ioat_domains(dn, dev->upstream, ri);
 		}
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 6274f02f61..5fc90e71a3 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -27,22 +27,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	mainboard_silicon_init_params(silupd);
 }
 
-#if CONFIG(HAVE_ACPI_TABLES)
-const char *soc_acpi_name(const struct device *dev)
-{
-	if (dev->path.type == DEVICE_PATH_DOMAIN)
-		return "PC00";
-	return NULL;
-}
-#endif
-
 static struct device_operations pci_domain_ops = {
 	.read_resources = iio_pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,
 	.scan_bus = iio_pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables  = &northbridge_write_acpi_tables,
-	.acpi_name        = soc_acpi_name
+	.acpi_name          = soc_acpi_name,
 #endif
 };
 
diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h
index 47c409036e..afccfe4a53 100644
--- a/src/soc/intel/xeon_sp/include/soc/acpi.h
+++ b/src/soc/intel/xeon_sp/include/soc/acpi.h
@@ -29,4 +29,6 @@ unsigned long acpi_fill_cedt(unsigned long current);
 unsigned long acpi_fill_hmat(unsigned long current);
 unsigned long cxl_fill_srat(unsigned long current);
 
+void iio_domain_set_acpi_name(struct device *dev, const char *prefix);
+
 #endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index 37277775ca..a010bd1bb2 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -15,6 +15,20 @@ union xeon_domain_path {
 	};
 };
 
+/*
+ * Every STACK can have multiple PCI domains with an unique domain type.
+ * This is only of cosmetic nature and generates more readable ACPI code,
+ * but isn't technical necessary.
+ */
+#define DOMAIN_TYPE_CPM0       "PM"
+#define DOMAIN_TYPE_CPM1       "PN"
+#define DOMAIN_TYPE_DINO       "DI"
+#define DOMAIN_TYPE_HQM0       "HQ"
+#define DOMAIN_TYPE_HQM1       "HR"
+#define DOMAIN_TYPE_PCIE       "PC"
+#define DOMAIN_TYPE_UBX0       "UC"
+#define DOMAIN_TYPE_UBX1       "UD"
+
 void iio_pci_domain_read_resources(struct device *dev);
 void iio_pci_domain_scan_bus(struct device *dev);
 void attach_iio_stacks(struct device *dev);
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 68737ed5b1..92663d96b2 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -13,22 +13,13 @@
 #include <soc/soc_util.h>
 #include <soc/util.h>
 
-#if CONFIG(HAVE_ACPI_TABLES)
-const char *soc_acpi_name(const struct device *dev)
-{
-	if (dev->path.type == DEVICE_PATH_DOMAIN)
-		return "PC00";
-	return NULL;
-}
-#endif
-
 static struct device_operations pci_domain_ops = {
 	.read_resources = iio_pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,
 	.scan_bus = iio_pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables  = &northbridge_write_acpi_tables,
-	.acpi_name        = soc_acpi_name
+	.acpi_name          = soc_acpi_name,
 #endif
 };
 
diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index d57b240ce3..cc3719d16d 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -8,6 +8,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <device/pciexp.h>
+#include <intelblocks/acpi.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
@@ -37,15 +38,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	mainboard_silicon_init_params(silupd);
 }
 
-#if CONFIG(HAVE_ACPI_TABLES)
-const char *soc_acpi_name(const struct device *dev);
-const char *soc_acpi_name(const struct device *dev)
-{
-	if (dev->path.type == DEVICE_PATH_DOMAIN)
-		return "PC00";
-	return NULL;
-}
-#endif
 
 static struct device_operations pci_domain_ops = {
 	.read_resources = iio_pci_domain_read_resources,
@@ -53,7 +45,7 @@ static struct device_operations pci_domain_ops = {
 	.scan_bus = iio_pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables = &northbridge_write_acpi_tables,
-	.acpi_name = soc_acpi_name
+	.acpi_name         = soc_acpi_name,
 #endif
 };
 
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c
index 0d81d0d2ef..5528efa6b6 100644
--- a/src/soc/intel/xeon_sp/spr/ioat.c
+++ b/src/soc/intel/xeon_sp/spr/ioat.c
@@ -8,6 +8,8 @@
 
 #include <defs_iio.h>
 #include <hob_iiouds.h>
+#include <intelblocks/acpi.h>
+#include <soc/acpi.h>
 #include <IioPcieConfigUpd.h>
 
 #include <soc/chip_common.h>
@@ -21,12 +23,16 @@ static struct device_operations ioat_domain_ops = {
 	.read_resources = noop_read_resources,
 	.set_resources = pci_domain_set_resources,
 	.scan_bus = pci_host_bridge_scan_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name        = soc_acpi_name,
+#endif
 };
 
 static void create_ioat_domain(const union xeon_domain_path dp, struct bus *const upstream,
 				const unsigned int bus_base, const unsigned int bus_limit,
 				const resource_t mem32_base, const resource_t mem32_limit,
-				const resource_t mem64_base, const resource_t mem64_limit)
+				const resource_t mem64_base, const resource_t mem64_limit,
+				const char *prefix)
 {
 	union xeon_domain_path new_path = {
 		.domain_path = dp.domain_path
@@ -44,6 +50,7 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons
 		die("%s: out of memory.\n", __func__);
 
 	domain->ops = &ioat_domain_ops;
+	iio_domain_set_acpi_name(domain, prefix);
 
 	struct bus *const bus = alloc_bus(domain);
 	bus->secondary = bus_base;
@@ -94,14 +101,16 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons
 	mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
 	bus_base = sr->BusBase + CPM_BUS_OFFSET;
 	bus_limit = bus_base + CPM_RESERVED_BUS;
-	create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+	create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit,
+			   DOMAIN_TYPE_CPM0);
 
 	/* HQM0 */
 	mem64_base = mem64_limit + 1;
 	mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
 	bus_base = sr->BusBase + HQM_BUS_OFFSET;
 	bus_limit = bus_base + HQM_RESERVED_BUS;
-	create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+	create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit,
+			   DOMAIN_TYPE_HQM0);
 
 	/* CPM1 (optional) */
 	mem64_base = mem64_limit + 1;
@@ -109,7 +118,8 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons
 	bus_base = sr->BusBase + CPM1_BUS_OFFSET;
 	bus_limit = bus_base + CPM_RESERVED_BUS;
 	if (bus_limit <= sr->BusLimit)
-		create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+		create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit,
+				   DOMAIN_TYPE_CPM1);
 
 	/* HQM1 (optional) */
 	mem64_base = mem64_limit + 1;
@@ -117,7 +127,8 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons
 	bus_base = sr->BusBase + HQM1_BUS_OFFSET;
 	bus_limit = bus_base + HQM_RESERVED_BUS;
 	if (bus_limit <= sr->BusLimit)
-		create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+		create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit,
+				   DOMAIN_TYPE_HQM1);
 
 	/* DINO */
 	mem64_base = mem64_limit + 1;
@@ -125,5 +136,5 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons
 	bus_base = sr->BusBase;
 	bus_limit = bus_base;
 	create_ioat_domain(path, bus, bus_base, bus_limit, sr->PciResourceMem32Base, sr->PciResourceMem32Limit,
-		mem64_base, mem64_limit);
+			   mem64_base, mem64_limit, DOMAIN_TYPE_DINO);
 }