diff options
| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-07-10 12:43:26 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 15:01:02 +0000 |
| commit | 3e52d7955f8741e4645d183e20f648d4523eb4c6 (patch) | |
| tree | 33c99996b6b2fd491d9182c563c9804df692c5b5 | |
| parent | ce3c77c30536649ba2a6ab81979a7fa371128c31 (diff) | |
mb/ibm/sbp1: Disable SIO Uarts
Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.
TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.
Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| -rw-r--r-- | src/mainboard/ibm/sbp1/bootblock.c | 3 | ||||
| -rw-r--r-- | src/mainboard/ibm/sbp1/devicetree.cb | 10 |
2 files changed, 2 insertions, 11 deletions
diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c index 9aca04e1ef..e04d8ef6be 100644 --- a/src/mainboard/ibm/sbp1/bootblock.c +++ b/src/mainboard/ibm/sbp1/bootblock.c @@ -28,7 +28,4 @@ void bootblock_mainboard_early_init(void) /* Enable com1 (0x3f8) and superio (0x2e) */ pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); - - const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); - aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb index 098fd9a8eb..99c14b17f5 100644 --- a/src/mainboard/ibm/sbp1/devicetree.cb +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -10,14 +10,8 @@ chip soc/intel/xeon_sp/spr device pnp 2e.0 on chip superio/aspeed/ast2400 register "use_espi" = "1" - device pnp 2e.2 on # SUART1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # SUART2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end + device pnp 2e.2 off end # SUART1 + device pnp 2e.3 off end # SUART2 end end end |