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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-11-10 16:08:37 -0700
committerAaron Durbin <adurbin@chromium.org>2017-11-13 17:21:56 +0000
commit3e4e4c5f88dbb65e789410048bcb83fcdb30c989 (patch)
treed7c1dad9977cd01f745f5dc77551618c07381014
parentc4f9f4bdae57a62ef14a526e51ce2b7d894a0682 (diff)
soc/amd/stoneyridge: Fix DRAM clear check
Explicitly add #include files to romstage.c to ensure sizes of the devicetree structures are correct. The AMD support headers have an open #pragma pack(1) which causes structure sizes to change based on include ordering in different compilation units. More concretely, this fixes a bug where dev->chip_info is incorrectly detected as 0. Also shorten a printk string to bring the source line within 80 columns. Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/amd/stoneyridge/romstage.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 06000ffd92..32dee5ab25 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -21,6 +21,8 @@
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h>
+#include <device/device.h>
+#include <chip.h>
#include <program_loading.h>
#include <agesawrapper.h>
#include <agesawrapper_call.h>
@@ -118,7 +120,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams)
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "ERROR: Could not find SoC devicetree config\n");
+ printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
/* In case of a BIOS error, only attempt to set UMA. */
PostParams->MemConfig.UmaMode = IS_ENABLED(CONFIG_GFXUMA) ?
UMA_AUTO : UMA_NONE;