diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-14 22:27:51 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-14 20:44:13 +0000 |
| commit | 3e314636a63e5f981eb038a2767bd606fea9f468 (patch) | |
| tree | 2c5c7127e1e72a9fdd7a0dee1f84da0fe6be0830 | |
| parent | b27b0fd2ac06e9aa8bafb8f780e5859da5bf6420 (diff) | |
soc/intel/skylake/cpu.c: Fix comment coding style
This comment does not follow any of the styles outlined in the coding
style page of the documentation. Adjust it to match the preferred style.
Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 79fcda1fa5..f1b40f6d01 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,10 +34,10 @@ static void configure_isst(void) if (conf->speed_shift_enable) { /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. coreboot needs to configure MSR 0x1AA - which is then reflected in the CPUID register. - */ + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ |