device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC

This patch adds new eSPI/LPC PCI device IDs for Intel PTL-U and PTL-H.

Additionally, updates the LPC driver's `pci_device_ids` list to
include these new IDs.

Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2

BUG=b:347669091
TEST=Able to build google/fatcat.

Change-Id: Ie9f0ea9536e2f73c2258e9e12b510d21212248ea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>

2 files changed, 128 insertions, 16 deletions

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 8eff32f0ec..7261dbdb28 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3168,14 +3168,70 @@
 #define PCI_DID_INTEL_LNL_ESPI_5			0xa805
 #define PCI_DID_INTEL_LNL_ESPI_6			0xa806
 #define PCI_DID_INTEL_LNL_ESPI_7			0xa807
-#define PCI_DID_INTEL_PTL_ESPI_0			0xe400
-#define PCI_DID_INTEL_PTL_ESPI_1			0xe401
-#define PCI_DID_INTEL_PTL_ESPI_2			0xe402
-#define PCI_DID_INTEL_PTL_ESPI_3			0xe403
-#define PCI_DID_INTEL_PTL_ESPI_4			0xe404
-#define PCI_DID_INTEL_PTL_ESPI_5			0xe405
-#define PCI_DID_INTEL_PTL_ESPI_6			0xe406
-#define PCI_DID_INTEL_PTL_ESPI_7			0xe407
+#define PCI_DID_INTEL_PTL_H_ESPI_0			0xe400
+#define PCI_DID_INTEL_PTL_H_ESPI_1			0xe401
+#define PCI_DID_INTEL_PTL_H_ESPI_2			0xe402
+#define PCI_DID_INTEL_PTL_H_ESPI_3			0xe403
+#define PCI_DID_INTEL_PTL_H_ESPI_4			0xe404
+#define PCI_DID_INTEL_PTL_H_ESPI_5			0xe405
+#define PCI_DID_INTEL_PTL_H_ESPI_6			0xe406
+#define PCI_DID_INTEL_PTL_H_ESPI_7			0xe407
+#define PCI_DID_INTEL_PTL_H_ESPI_8			0xe408
+#define PCI_DID_INTEL_PTL_H_ESPI_9			0xe409
+#define PCI_DID_INTEL_PTL_H_ESPI_10			0xe40a
+#define PCI_DID_INTEL_PTL_H_ESPI_11			0xe40b
+#define PCI_DID_INTEL_PTL_H_ESPI_12			0xe40c
+#define PCI_DID_INTEL_PTL_H_ESPI_13			0xe40d
+#define PCI_DID_INTEL_PTL_H_ESPI_14			0xe40e
+#define PCI_DID_INTEL_PTL_H_ESPI_15			0xe40f
+#define PCI_DID_INTEL_PTL_H_ESPI_16			0xe410
+#define PCI_DID_INTEL_PTL_H_ESPI_17			0xe411
+#define PCI_DID_INTEL_PTL_H_ESPI_18			0xe412
+#define PCI_DID_INTEL_PTL_H_ESPI_19			0xe413
+#define PCI_DID_INTEL_PTL_H_ESPI_20			0xe414
+#define PCI_DID_INTEL_PTL_H_ESPI_21			0xe415
+#define PCI_DID_INTEL_PTL_H_ESPI_22			0xe416
+#define PCI_DID_INTEL_PTL_H_ESPI_23			0xe417
+#define PCI_DID_INTEL_PTL_H_ESPI_24			0xe418
+#define PCI_DID_INTEL_PTL_H_ESPI_25			0xe419
+#define PCI_DID_INTEL_PTL_H_ESPI_26			0xe41a
+#define PCI_DID_INTEL_PTL_H_ESPI_27			0xe41b
+#define PCI_DID_INTEL_PTL_H_ESPI_28			0xe41c
+#define PCI_DID_INTEL_PTL_H_ESPI_29			0xe41d
+#define PCI_DID_INTEL_PTL_H_ESPI_30			0xe41e
+#define PCI_DID_INTEL_PTL_H_ESPI_31			0xe41f
+#define PCI_DID_INTEL_PTL_U_H_ESPI_0			0xe300
+#define PCI_DID_INTEL_PTL_U_H_ESPI_1			0xe301
+#define PCI_DID_INTEL_PTL_U_H_ESPI_2			0xe302
+#define PCI_DID_INTEL_PTL_U_H_ESPI_3			0xe303
+#define PCI_DID_INTEL_PTL_U_H_ESPI_4			0xe304
+#define PCI_DID_INTEL_PTL_U_H_ESPI_5			0xe305
+#define PCI_DID_INTEL_PTL_U_H_ESPI_6			0xe306
+#define PCI_DID_INTEL_PTL_U_H_ESPI_7			0xe307
+#define PCI_DID_INTEL_PTL_U_H_ESPI_8			0xe308
+#define PCI_DID_INTEL_PTL_U_H_ESPI_9			0xe309
+#define PCI_DID_INTEL_PTL_U_H_ESPI_10			0xe30a
+#define PCI_DID_INTEL_PTL_U_H_ESPI_11			0xe30b
+#define PCI_DID_INTEL_PTL_U_H_ESPI_12			0xe30c
+#define PCI_DID_INTEL_PTL_U_H_ESPI_13			0xe30d
+#define PCI_DID_INTEL_PTL_U_H_ESPI_14			0xe30e
+#define PCI_DID_INTEL_PTL_U_H_ESPI_15			0xe30f
+#define PCI_DID_INTEL_PTL_U_H_ESPI_16			0xe310
+#define PCI_DID_INTEL_PTL_U_H_ESPI_17			0xe311
+#define PCI_DID_INTEL_PTL_U_H_ESPI_18			0xe312
+#define PCI_DID_INTEL_PTL_U_H_ESPI_19			0xe313
+#define PCI_DID_INTEL_PTL_U_H_ESPI_20			0xe314
+#define PCI_DID_INTEL_PTL_U_H_ESPI_21			0xe315
+#define PCI_DID_INTEL_PTL_U_H_ESPI_22			0xe316
+#define PCI_DID_INTEL_PTL_U_H_ESPI_23			0xe317
+#define PCI_DID_INTEL_PTL_U_H_ESPI_24			0xe318
+#define PCI_DID_INTEL_PTL_U_H_ESPI_25			0xe319
+#define PCI_DID_INTEL_PTL_U_H_ESPI_26			0xe31a
+#define PCI_DID_INTEL_PTL_U_H_ESPI_27			0xe31b
+#define PCI_DID_INTEL_PTL_U_H_ESPI_28			0xe31c
+#define PCI_DID_INTEL_PTL_U_H_ESPI_29			0xe31d
+#define PCI_DID_INTEL_PTL_U_H_ESPI_30			0xe31e
+#define PCI_DID_INTEL_PTL_U_H_ESPI_31			0xe31f
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 0b8c722a69..147c4f1621 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -141,14 +141,70 @@ struct device_operations lpc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DID_INTEL_PTL_ESPI_0,
-	PCI_DID_INTEL_PTL_ESPI_1,
-	PCI_DID_INTEL_PTL_ESPI_2,
-	PCI_DID_INTEL_PTL_ESPI_3,
-	PCI_DID_INTEL_PTL_ESPI_4,
-	PCI_DID_INTEL_PTL_ESPI_5,
-	PCI_DID_INTEL_PTL_ESPI_6,
-	PCI_DID_INTEL_PTL_ESPI_7,
+	PCI_DID_INTEL_PTL_U_H_ESPI_0,
+	PCI_DID_INTEL_PTL_U_H_ESPI_1,
+	PCI_DID_INTEL_PTL_U_H_ESPI_2,
+	PCI_DID_INTEL_PTL_U_H_ESPI_3,
+	PCI_DID_INTEL_PTL_U_H_ESPI_4,
+	PCI_DID_INTEL_PTL_U_H_ESPI_5,
+	PCI_DID_INTEL_PTL_U_H_ESPI_6,
+	PCI_DID_INTEL_PTL_U_H_ESPI_7,
+	PCI_DID_INTEL_PTL_U_H_ESPI_8,
+	PCI_DID_INTEL_PTL_U_H_ESPI_9,
+	PCI_DID_INTEL_PTL_U_H_ESPI_10,
+	PCI_DID_INTEL_PTL_U_H_ESPI_11,
+	PCI_DID_INTEL_PTL_U_H_ESPI_12,
+	PCI_DID_INTEL_PTL_U_H_ESPI_13,
+	PCI_DID_INTEL_PTL_U_H_ESPI_14,
+	PCI_DID_INTEL_PTL_U_H_ESPI_15,
+	PCI_DID_INTEL_PTL_U_H_ESPI_16,
+	PCI_DID_INTEL_PTL_U_H_ESPI_17,
+	PCI_DID_INTEL_PTL_U_H_ESPI_18,
+	PCI_DID_INTEL_PTL_U_H_ESPI_19,
+	PCI_DID_INTEL_PTL_U_H_ESPI_20,
+	PCI_DID_INTEL_PTL_U_H_ESPI_21,
+	PCI_DID_INTEL_PTL_U_H_ESPI_22,
+	PCI_DID_INTEL_PTL_U_H_ESPI_23,
+	PCI_DID_INTEL_PTL_U_H_ESPI_24,
+	PCI_DID_INTEL_PTL_U_H_ESPI_25,
+	PCI_DID_INTEL_PTL_U_H_ESPI_26,
+	PCI_DID_INTEL_PTL_U_H_ESPI_27,
+	PCI_DID_INTEL_PTL_U_H_ESPI_28,
+	PCI_DID_INTEL_PTL_U_H_ESPI_29,
+	PCI_DID_INTEL_PTL_U_H_ESPI_30,
+	PCI_DID_INTEL_PTL_U_H_ESPI_31,
+	PCI_DID_INTEL_PTL_H_ESPI_0,
+	PCI_DID_INTEL_PTL_H_ESPI_1,
+	PCI_DID_INTEL_PTL_H_ESPI_2,
+	PCI_DID_INTEL_PTL_H_ESPI_3,
+	PCI_DID_INTEL_PTL_H_ESPI_4,
+	PCI_DID_INTEL_PTL_H_ESPI_5,
+	PCI_DID_INTEL_PTL_H_ESPI_6,
+	PCI_DID_INTEL_PTL_H_ESPI_7,
+	PCI_DID_INTEL_PTL_H_ESPI_8,
+	PCI_DID_INTEL_PTL_H_ESPI_9,
+	PCI_DID_INTEL_PTL_H_ESPI_10,
+	PCI_DID_INTEL_PTL_H_ESPI_11,
+	PCI_DID_INTEL_PTL_H_ESPI_12,
+	PCI_DID_INTEL_PTL_H_ESPI_13,
+	PCI_DID_INTEL_PTL_H_ESPI_14,
+	PCI_DID_INTEL_PTL_H_ESPI_15,
+	PCI_DID_INTEL_PTL_H_ESPI_16,
+	PCI_DID_INTEL_PTL_H_ESPI_17,
+	PCI_DID_INTEL_PTL_H_ESPI_18,
+	PCI_DID_INTEL_PTL_H_ESPI_19,
+	PCI_DID_INTEL_PTL_H_ESPI_20,
+	PCI_DID_INTEL_PTL_H_ESPI_21,
+	PCI_DID_INTEL_PTL_H_ESPI_22,
+	PCI_DID_INTEL_PTL_H_ESPI_23,
+	PCI_DID_INTEL_PTL_H_ESPI_24,
+	PCI_DID_INTEL_PTL_H_ESPI_25,
+	PCI_DID_INTEL_PTL_H_ESPI_26,
+	PCI_DID_INTEL_PTL_H_ESPI_27,
+	PCI_DID_INTEL_PTL_H_ESPI_28,
+	PCI_DID_INTEL_PTL_H_ESPI_29,
+	PCI_DID_INTEL_PTL_H_ESPI_30,
+	PCI_DID_INTEL_PTL_H_ESPI_31,
 	PCI_DID_INTEL_LNL_ESPI_0,
 	PCI_DID_INTEL_LNL_ESPI_1,
 	PCI_DID_INTEL_LNL_ESPI_2,