diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2022-02-21 11:44:47 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-23 15:05:40 +0000 |
| commit | 3a3920263ac316982696cbcdef639e0f77323f00 (patch) | |
| tree | 374413e49821d51a1e0dadc072c54de2a5080ed6 | |
| parent | eee62c153774e503ceeba08aedacd03411755250 (diff) | |
soc/mediatek/mt8186: disable VSRAM_CORE
VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.
BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/mediatek/mt8186/mt6366.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 90ff3287d4..b993a9256a 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -167,6 +167,10 @@ static struct pmic_setting init_setting[] = { {0x1BCC, 0x70F, 0x7F7F, 0}, {0x1C9E, 0x38, 0x7F, 0}, {0x1CA0, 0x70F, 0x7F7F, 0}, + /* VSRAM_CORE: set SW mode */ + {0x1CA4, 0x1, 0xFFFF, 0}, + /* VSRAM_CORE: SW set OFF */ + {0x1C9C, 0x0, 0xFFFF, 0}, {0x1EA2, 0x1B, 0x1F, 0}, {0x1EA4, 0xC00, 0x1C00, 0}, {0x1EA6, 0xC00, 0x1C00, 0}, |