diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-12 14:37:43 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-14 18:05:17 +0000 |
| commit | 394c6b092251f0da8f0bd159e0eb08a41a6e4afc (patch) | |
| tree | e9d347574e889fc911ebe512d2bfc012239a5d73 | |
| parent | 844775059d8cb456dec988e6378f3a73ea730001 (diff) | |
soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/amd/common/block/cpu/Kconfig | 13 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/update_microcode.c (renamed from src/soc/amd/picasso/update_microcode.c) | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 1 |
5 files changed, 22 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 996605e7f3..f418ee7cc5 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -44,3 +44,16 @@ config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H Select this option to add the common functions for getting the TSC frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC- based monotonic timer functionality to the build. + +config SOC_AMD_COMMON_BLOCK_UCODE + bool + select SUPPORT_CPU_UCODE_IN_CBFS + default n + help + Builds in support for loading uCode. + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + int + depends on SOC_AMD_COMMON_BLOCK_UCODE + help + Defines the size of the uCode binary in bytes. diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 4c0266396c..f402e703c9 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1 +1,2 @@ subdirs-y += ./* +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c diff --git a/src/soc/amd/picasso/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 47a98353b9..2ba180298c 100644 --- a/src/soc/amd/picasso/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -8,7 +8,10 @@ #include <cpu/amd/msr.h> #include <cbfs.h> -#define MPB_MAX_SIZE 3200 +_Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0, + "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set"); + +#define MPB_MAX_SIZE CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE #define MPB_DATA_OFFSET 32 struct microcode { diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d037d48990..16a12972b4 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -58,7 +59,9 @@ config CPU_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select UDK_2017_BINDING select HAVE_CF9_RESET - select SUPPORT_CPU_UCODE_IN_CBFS + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 3200 config FSP_M_FILE string "FSP-M (memory init) binary path and filename" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 99e2da1040..d2a5e4c393 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -48,7 +48,6 @@ ramstage-y += uart.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += fsp_params.c -ramstage-y += update_microcode.c ramstage-y += graphics.c ramstage-y += pcie_gpp.c ramstage-y += xhci.c |