diff options
| author | Chris.Wang <chris.wang@amd.corp-partner.google.com> | 2022-04-18 22:51:42 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-19 12:15:04 +0000 |
| commit | 38f7ba3db42a64bf9ddfdf29d3d90723486776d4 (patch) | |
| tree | 9b70ee3421d20d4352601a847398653b693c9de1 | |
| parent | d643165c64ef89c72e4e004abe7a7675f90b0955 (diff) | |
mb/google/guybrush/var/dewatt: Update APU STT setting
update STT setting for dewatt.
BUG=b:228040295
BRANCH=guybrush
TEST=build, verify the parameter has been applied to
the system by checking the AGT tool.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/mainboard/google/guybrush/variants/dewatt/overridetree.cb | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index 866aee5932..84bf9da25a 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -27,6 +27,28 @@ chip soc/amd/cezanne register "telemetry_vddcrsocfull_scale_current_mA" = "29785" #mA register "telemetry_vddcrsocoffset" = "461" + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "15000" + register "stt_m1" = "0x022B" + register "stt_m2" = "0x117" + register "stt_m3" = "0" + register "stt_m4" = "0" + register "stt_m5" = "0" + register "stt_m6" = "0" + register "stt_c_apu" = "0xBA4" + register "stt_c_gpu" = "0" + register "stt_c_hs2" = "0" + register "stt_alpha_apu" = "0x199A" + register "stt_alpha_gpu" = "0" + register "stt_alpha_hs2" = "0" + register "stt_skin_temp_apu" = "0x2D00" + register "stt_skin_temp_gpu" = "0" + register "stt_skin_temp_hs2" = "0" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0x2666" + #USB 2/3 phy config register "usb_phy" = "{ /* Left USB C0 Port */ |