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authorKenneth Chan <kenneth.chan@quanta.corp-partner.google.com>2021-12-08 18:56:50 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-12-13 14:03:04 +0000
commit38afe9e31c72279a58e337f48b828e4165c601f3 (patch)
tree77a7bbb8901dc2b0fa21b590bc6c5b93d012d6c2
parentd76d2e275fb5d36ddd2357d63f8992f586a2d039 (diff)
mb/google/guybrush/var/dewatt: Add Elan touchscreen
Add Elan 6918 touchscreen for dewatt. (EKTH6918 Product Spec V0.5) BUG=b:208373433 TEST=emerge-guybrush coreboot chromeos-bootimage. Teseted with Elan 6918 touchscreen. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
-rw-r--r--src/mainboard/google/guybrush/variants/dewatt/overridetree.cb19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
index bbcb79c40c..a1614c9e03 100644
--- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
@@ -63,4 +63,23 @@ chip soc/amd/cezanne
device i2c 2c on end
end
end # I2C0
+ device ref i2c_1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN6918""
+ register "generic.desc" = ""ELAN Touchscreen""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)"
+ register "generic.reset_delay_ms" = "20"
+ register "generic.reset_off_delay_ms" = "2"
+ register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_120)"
+ register "generic.stop_off_delay_ms" = "2"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)"
+ register "generic.enable_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 10 on end
+ end
+ end # I2C1
end # chip soc/amd/cezanne