diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-08-12 13:51:22 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 12:02:50 +0100 |
| commit | 3106d0ffce85fe07feefb5c488802aab8e9b42f6 (patch) | |
| tree | 7e99d9f46e99991bd7571500aa89460ecc2e690f | |
| parent | 4fb3a61fc6e11686a95c09f63e194fba0cb899f6 (diff) | |
haswell: Misc updates from 1.6.1 ref code
These programming sequences were changed in the latest code.
Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 21 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 3 |
2 files changed, 6 insertions, 18 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f13ef7a62d..00d7583048 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -350,20 +350,11 @@ static void gma_pm_init_post_vbios(struct device *dev) gpu_is_ulx = 1; /* CD Frequency */ - if (gtt_read(0x42014) & 0x1000000) { - cdclk = 0; /* only 450mhz */ - } else { - cdclk = 2; /* 337.5mhz, 450mhz, or 540mhz */ - if (gpu_is_ulx) - cdclk = 0; /* only 337.5mhz */ - - /* TODO: this check does not seem right... */ - if (haswell_is_ult() && - haswell_stepping() < HASWELL_STEPPING_MOBILE_D0) - cdclk = 0; /* only 450mhz */ - else - cdclk = 1; /* 337.5mhz and 450mhz */ - } + if ((gtt_read(0x42014) & 0x1000000) || gpu_is_ulx || haswell_is_ult()) + cdclk = 0; /* fixed frequency */ + else + cdclk = 2; /* variable frequency */ + if (gpu_is_ulx || cdclk != 0) gtt_rmw(0x130040, 0xf7ffffff, 0x04000000); else @@ -371,7 +362,7 @@ static void gma_pm_init_post_vbios(struct device *dev) /* More magic */ if (haswell_is_ult() || gpu_is_ulx) { - if (cdclk == 1 && gpu_is_ulx == 0) + if (!gpu_is_ulx) gtt_write(0x138128, 0x00000000); else gtt_write(0x138128, 0x00000001); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 6a4d75cac2..581b79d1a4 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -649,9 +649,6 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set undocumented bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 12) | (1 << 6)); - /* Set Invalid Recieve Range Check Enable in MPC register. */ pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); |