diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-07 22:04:13 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-12 18:26:34 +0000 |
| commit | 2f58bbd686088597aa33f1b44450957443cd8714 (patch) | |
| tree | c7a31b7b015e26b0df7744abaf7165f94b6a0923 | |
| parent | 5f6cf6105c701f017c1a194710b05bba2756d003 (diff) | |
soc/amd/genoa: Parse APOB for DRAM layout
Use the xPRF call to report holes in memory and report those regions as
reserved.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5605499e39931e1a1592318310112666f8a0f144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
| -rw-r--r-- | src/soc/amd/genoa/domain.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/amd/genoa/domain.c b/src/soc/amd/genoa/domain.c index 43e436a00a..e42823009d 100644 --- a/src/soc/amd/genoa/domain.c +++ b/src/soc/amd/genoa/domain.c @@ -8,8 +8,22 @@ #include <device/device.h> #include <types.h> +#include <vendorcode/amd/opensil/genoa_poc/opensil.h> + #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0 +static void genoa_domain_read_resources(struct device *domain) +{ + amd_pci_domain_read_resources(domain); + + // We only want to add the DRAM memory map once + if (domain->link_list->secondary == 0) { + /* 0x1000 is a large enough first index to be sure to not overlap with the + resources added by amd_pci_domain_read_resources */ + add_opensil_memmap(domain, 0x1000); + } +} + static void genoa_domain_set_resources(struct device *domain) { if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -35,7 +49,7 @@ static void genoa_domain_set_resources(struct device *domain) } struct device_operations genoa_pci_domain_ops = { - .read_resources = amd_pci_domain_read_resources, + .read_resources = genoa_domain_read_resources, .set_resources = genoa_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, }; |