diff options
| author | Marc Jones <marc.jones@amd.com> | 2008-05-16 18:08:54 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-05-16 18:08:54 +0000 |
| commit | 2ee5c9e21b6f2b3f7a76f27b90bd8f4b240839c7 (patch) | |
| tree | f4f3cb1801e2f21cf80c9023de93ac281d262c09 | |
| parent | 0fd8ccd7e71772c9827bffd5632ec4f218e26783 (diff) | |
Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/amd/db800/Config.lb | 4 | ||||
| -rw-r--r-- | src/mainboard/digitallogic/msm800sev/Config.lb | 4 | ||||
| -rw-r--r-- | src/mainboard/iei/pcisa-lx-800-r10/Config.lb | 4 | ||||
| -rw-r--r-- | src/mainboard/pcengines/alix1c/Config.lb | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb index bdc109369f..2c0cce3e1e 100644 --- a/src/mainboard/amd/db800/Config.lb +++ b/src/mainboard/amd/db800/Config.lb @@ -127,8 +127,8 @@ chip northbridge/amd/lx # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000010da" - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb index 84db58bb42..eceee5bf49 100644 --- a/src/mainboard/digitallogic/msm800sev/Config.lb +++ b/src/mainboard/digitallogic/msm800sev/Config.lb @@ -128,9 +128,9 @@ chip northbridge/amd/lx # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # How to get these? Boot linux and do this: # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_enable" = "0x0000105a" # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_polarity" = "0x0000EFA5" # mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" # Don't yet know how to find this. diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb index 7c89aaffca..87aa03d741 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb @@ -78,8 +78,8 @@ chip northbridge/amd/lx # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000010da" - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb index c78587851b..73a1875280 100644 --- a/src/mainboard/pcengines/alix1c/Config.lb +++ b/src/mainboard/pcengines/alix1c/Config.lb @@ -148,9 +148,9 @@ chip northbridge/amd/lx # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # How to get these? Boot linux and do this: # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_enable" = "0x0000105a" # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_polarity" = "0x0000EFA5" # mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" # Don't yet know how to find this. |