diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-29 01:38:58 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-01 00:50:21 +0200 |
| commit | 2bb1d30d69d807ee70d005b70f8ea5e9caa74fae (patch) | |
| tree | 5f263164ab462601692e9a82f0f94ddb3ceedd9b | |
| parent | 29dd5da1dc577bf97cb85998b17b2e163a5ab86e (diff) | |
nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
During receiver enable cycle training on Family 15h the entire range
of possible delays is searched, even though the single passing window
is often found nearly immediately. Skip the remainder of the delay
range after the passing window has been located.
Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14544
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 7ef2900de1..69a5fe3fe0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1617,6 +1617,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t rx_en_offset; uint8_t internal_lane; uint8_t dct_training_success; + uint8_t lane_success_count; uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; @@ -1695,6 +1696,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { /* Initialize variables */ memset(dqs_results_array, 0, sizeof(dqs_results_array)); + lane_success_count = 0; /* 2.10.5.8.3 (1) */ dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8)); @@ -1721,6 +1723,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 (4 B) */ dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); + + if (dqs_results_array[current_phy_phase_delay[lane]]) + lane_success_count++; + + /* Don't bother testing larger values if the end of the passing window was already found */ + if (!dqs_results_array[current_phy_phase_delay[lane]] && (lane_success_count > 1)) + break; } uint16_t phase_delay; |