diff options
| author | Nick Vaccaro <nvaccaro@chromium.org> | 2017-12-20 16:48:17 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-11 01:08:39 +0000 |
| commit | 2baf49fa67ee237e527e92b6de4706d3df97b5c6 (patch) | |
| tree | 072f7b659bb041e35fe891fa8f512c90f0b07441 | |
| parent | 8508f7d18286ca9207151951e28578d461cc799d (diff) | |
mainboard/google/zoombini/variants/meowth: fix gpio settings
-change GPP_C12 (H1 IRQ) to use GPI_SCI_LOW and level triggered
-set gspi gpios to no connects if CONFIG_ZOOMBINI_USE_SPI_TPM not set
BUG=b:69011806
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' succeeds
Change-Id: Ida1d1050db12982c3c497656162cc84c62a77f70
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/gpio.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index 39c2605a04..8ceb6e88b5 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -98,8 +98,8 @@ static const struct pad_config gpio_table[] = { NF1), /* UART_PCH_TX_DEBUG_RX */ /* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 0, DEEP), /* PP3300_TOUCH_EN */ /* UART0_CTS# */ PAD_NC(GPP_C11, NONE), -/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE, - INVERT), /* H1_PCH_INT_ODL */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, + LEVEL), /* H1_PCH_INT_ODL */ /* UART1_TXD */ PAD_NC(GPP_C13, NONE), /* UART1_RTS# */ PAD_CFG_GPI_SCI(GPP_C14, NONE, DEEP, EDGE_SINGLE, NONE), /* TOUCHSCREEN_INT_ODL */ @@ -265,9 +265,13 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ +#else +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), #endif -/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE, - INVERT), /* H1_PCH_INT_ODL */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, LEVEL), }; const struct pad_config *variant_gpio_table(size_t *num) |