diff options
| author | Shelley Chen <shchen@chromium.org> | 2018-02-06 21:16:04 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-02-07 20:41:37 +0000 |
| commit | 2a9e8124e19a1a9143b9461d1f1f114e8e751c8a (patch) | |
| tree | a5f3fde475cac2177fd87ec64b48fa68e663a258 | |
| parent | dc4bc06bb78ec96761bedefcd32c0c74544f2ea1 (diff) | |
mb/google/fizz: Set Pmax to 120 for all SKUs
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.
BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp
Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 9fb366df43..3b084ff1f9 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -285,6 +285,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_psyspl2" = "90" + register "psys_pmax" = "120" register "tcc_offset" = "6" # TCC of 94C # Use default SD card detect GPIO configuration |