diff options
| author | Michał Kopeć <michal.kopec@3mdeb.com> | 2022-11-28 13:10:40 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-02-16 19:33:13 +0000 |
| commit | 28daa6b9ae09af8caadee5ff251e1a7d6cd721fb (patch) | |
| tree | 270804fa1cd5dcc0e061bf6d8fbc2b59c4681004 | |
| parent | 3f9613bf6dbf84313b46c3ca364457e28bc00008 (diff) | |
soc/intel/elkhartlake/fsp_params.c: wire up remaining ddc params
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I434c22cd784e24c76bc47aee8728d28255b762db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 15 |
2 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 8743eb0871..b15d78a1ee 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -338,6 +338,7 @@ struct soc_intel_elkhartlake_config { */ uint8_t DdiPortAConfig; uint8_t DdiPortBConfig; + uint8_t DdiPortCConfig; /* Enable(1)/Disable(0) HPD */ uint8_t DdiPortAHpd; diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 8d802f42be..11fc2d3f75 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -259,10 +259,23 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); /* Display config */ + params->DdiPortAConfig = config->DdiPortAConfig; + params->DdiPortBConfig = config->DdiPortBConfig; + params->DdiPortCConfig = config->DdiPortCConfig; params->DdiPortAHpd = config->DdiPortAHpd; - params->DdiPortADdc = config->DdiPortADdc; + params->DdiPortBHpd = config->DdiPortBHpd; params->DdiPortCHpd = config->DdiPortCHpd; + params->DdiPort1Hpd = config->DdiPort1Hpd; + params->DdiPort2Hpd = config->DdiPort2Hpd; + params->DdiPort3Hpd = config->DdiPort3Hpd; + params->DdiPort4Hpd = config->DdiPort4Hpd; + params->DdiPortADdc = config->DdiPortADdc; + params->DdiPortBDdc = config->DdiPortBDdc; params->DdiPortCDdc = config->DdiPortCDdc; + params->DdiPort1Ddc = config->DdiPort1Ddc; + params->DdiPort2Ddc = config->DdiPort2Ddc; + params->DdiPort3Ddc = config->DdiPort3Ddc; + params->DdiPort4Ddc = config->DdiPort4Ddc; /* Intel Speed Step */ params->Eist = config->eist_enable; |