cpu/x86/mtrr: move cache_ramstage() to its only user

The Intel i3100 northbridge code is the only user of
cache_ramstage(). Therefore, place it next to the sole
consumer.

Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14097
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 9 insertions, 11 deletions

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 2e31a6e113..3d7ad11720 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -20,14 +20,6 @@ void set_var_mtrr(
 }
 
 #if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
-static void cache_ramstage(void)
-{
-	/* Enable caching for lower 1MB and ram stage using variable mtrr */
-	disable_cache();
-	set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
-	enable_cache();
-}
-
 const int addr_det = 0;
 
 /* the fixed and variable MTRRs are power-up with random values,
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index b426cb8043..53bf17c8d2 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -926,6 +926,13 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 	write32(MCBAR+0x154, recenb);
 }
 
+static void cache_ramstage(void)
+{
+	/* Enable caching for lower 1MB and ram stage using variable mtrr */
+	disable_cache();
+	set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+	enable_cache();
+}
 
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
@@ -1189,7 +1196,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	pci_write_config16(ctrl->f0, MCHSCRB, data16);
 
 	/* The memory is now setup, use it */
-#if !CONFIG_CACHE_AS_RAM
-	cache_ramstage();
-#endif
+	if (!IS_ENABLED(CONFIG_CACHE_AS_RAM))
+		cache_ramstage();
 }