diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2022-02-24 06:50:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-02 18:25:54 +0000 |
| commit | 257e2507faa797b0fdcd2ae4641a1a20e37db4b3 (patch) | |
| tree | d112ea8ceca62a62ae8f70ff727553aca663ecee | |
| parent | 03575db36aa95ac1b8919ae7c8064768e6e423df (diff) | |
mb/siemens/mc_ehl: Disable HS400 mode for eMMC
In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.
Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 87b455fd83..d7c3e22f3b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -84,7 +84,7 @@ chip soc/intel/elkhartlake register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 438419a233..ffcf1da9fe 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -69,7 +69,7 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[6]" = "true" # Storage (SDCARD/EMMC) related UPDs - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" |