diff options
| author | Martin Roth <martinroth@google.com> | 2018-01-11 16:14:39 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-13 23:45:27 +0000 |
| commit | 2572153aefbb8def000cddea973c34be5829c63d (patch) | |
| tree | 2668f9212c1bf9b43ffa2009b1f98ebba8b4cfa8 | |
| parent | 883de54fed25aebe3e68418adc63e7d54b400f91 (diff) | |
soc/amd/stoneyridge: Add definition for GENINT_DISABLE
BUG=b:71867096
TEST=None
Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index bbf6344f6a..d9016bc427 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -93,6 +93,7 @@ #define PM_HUD_SD_FLASH_CTRL 0xe7 #define PM_YANG_SD_FLASH_CTRL 0xe8 #define PM_PCIB_CFG 0xea +#define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) |