diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-06-23 19:40:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-06-26 12:56:00 +0000 |
| commit | 249aede238050e6a6ab71d3c6fb72aa5b5d4e78f (patch) | |
| tree | 95488295f64a28e5ea75b75bc1013b3f3bda978b | |
| parent | 80254118ac73233485d5d01b174036429c80282d (diff) | |
mb/google/rex: Avoid LPDDR5/x hang
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 5297ce28f4..0d639e3731 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -41,7 +41,7 @@ chip soc/intel/meteorlake register "sagv" = "SAGV_ENABLED" - register "sagv_freq_mhz[0]" = "2133" + register "sagv_freq_mhz[0]" = "3200" register "sagv_gear[0]" = "4" register "sagv_freq_mhz[1]" = "6000" |