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authorMathew King <mathewk@chromium.org>2021-04-14 15:29:44 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-04-16 06:52:02 +0000
commit23cc165d6a02020ff408bdcc56a07cd9dc9a2105 (patch)
tree86f7bca27aac7b0412bd0d5587828c1c9519dc22
parent9623f7bb1cd2c69bf8cab22cdd9ad41a25c674dc (diff)
soc/amd/cezanne: Add modern standby option to chip config
BUG=b:178728116 Change-Id: I0d09bd4361f5f47360daf750efbc993010804902 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/soc/amd/cezanne/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 76ecbfa057..b2c346252b 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -11,6 +11,9 @@ struct soc_amd_cezanne_config {
struct soc_amd_common_config common_config;
u8 i2c_scl_reset;
struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
+
+ /* Enable S0iX support */
+ bool s0ix_enable;
};
#endif /* CEZANNE_CHIP_H */