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authorSubrata Banik <subratabanik@google.com>2024-07-19 11:35:43 +0530
committerSubrata Banik <subratabanik@google.com>2024-07-22 17:31:00 +0000
commit23990df9196aac90adc46527edf260e0772da4eb (patch)
treefb99ed67d5d5cf1ddff16a6107cfcd9b09f0f428
parent5ad528a10ab2e5b5b3070cb25ef1e774f8d2da5b (diff)
mb/google/brya/var/trulo: Configure early and romstage GPIOs
This change adds early and romstage GPIO configurations for the trulo variant, including: Early GPIOs: - GSC (Google Security Controller) - WP (Write Protect) - UART0 (for serial debug) Romstage GPIOs: - Touch Screen early power sequencing CrOS GPIOs: - CROS_GPIO_VIRTUAL - GPIO_PCH_WP BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/brya/variants/trulo/gpio.c24
1 files changed, 21 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index 1a6d1b1466..fac17406d1 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -16,12 +16,29 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
- /* TODO */
+ /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
+ /* E3 : PROC_GP0 ==> SOC_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
+ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
};
/* Fill romstage gpio configuration */
static const struct pad_config romstage_gpio_table[] = {
- /* TODO */
+ /* Enable touchscreen, hold in reset */
+ /* E17 : GPP_E17 ==> SOC_TS_PWR_EN */
+ PAD_CFG_GPO(GPP_E17, 1, DEEP),
+ /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */
+ PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_gpio_table(size_t *num)
@@ -43,7 +60,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
}
static const struct cros_gpio cros_gpios[] = {
- /* TODO */
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
DECLARE_CROS_GPIOS(cros_gpios);