diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-29 09:30:23 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-28 20:15:28 +0000 |
| commit | 22f54c5a81bf387edcd7ea792bc1717c554054c6 (patch) | |
| tree | 82d5b1ba80b9046594393590f84ac677e2f0ac29 | |
| parent | 3a649eec28b9440a628626a7b882a9fb185a9a4a (diff) | |
amd/stoneyridge: Add NV storage to ramtop
The scratch registers in northbridge used for storing the top of
cacheable memory are volatile. Use the BiosRam storage in the FCH
instead.
TEST=Suspend and resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/ramtop.c | 10 |
3 files changed, 8 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index e043caf63a..9f99c3c58d 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -47,6 +47,7 @@ bootblock-y += reset.c bootblock-y += sb_util.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c +bootblock-y += sb_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -76,6 +77,7 @@ verstage-y += tsc_freq.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c +postcar-y += sb_util.c ramstage-y += BiosCallOuts.c ramstage-y += i2c.c diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index ccedcce7b4..2319b883d7 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -66,4 +66,7 @@ #define AMD_GPIO_MUX (AMD_SB_ACPI_MMIO_ADDR + 0x00000d00) #define AMD_GPIO_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x00001500) +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ + #endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 8268477a32..e676465ce7 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -22,20 +22,16 @@ #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <soc/northbridge.h> - -#define CBMEM_TOP_SCRATCHPAD 0x78 +#include <soc/southbridge.h> void backup_top_of_low_cacheable(uintptr_t ramtop) { - uint16_t top_cache = ramtop >> 16; - pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); } uintptr_t restore_top_of_low_cacheable(void) { - uint16_t top_cache; - top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); + return biosram_read32(BIOSRAM_CBMEM_TOP); } void *cbmem_top(void) |