diff options
| author | Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com> | 2021-11-16 15:02:07 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-12-06 12:31:42 +0000 |
| commit | 21d7d75796d4a9f71c7bab8716bdaa3c456451c8 (patch) | |
| tree | c9fec27bff366c3500de7950eaf264cbfc550530 | |
| parent | 461ff1d3e653bee655e1afe32c1dc5ada80fab6c (diff) | |
mb/var/gimble: Set PsysPmax to 143 W
This patch adds the setting of PsysPmax to 143 W according to
gimble board design.
BUG=b:206990759
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 47e81d8687..27ea5aa3bd 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -32,6 +32,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "143" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram |