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authorJonathan Zhang <jonzhang@fb.com>2021-04-28 09:23:22 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-05-10 20:31:19 +0000
commit206dfbf17349485e1f6d9e8351277edb673a5d24 (patch)
tree2cee78dfd4dd7e330fcfe4a741846c9e77e16f24
parent8618cf1edc68121e420d9a82483cc351040fd487 (diff)
doc/relnotes/4.14: add Intel Xeon-SP support status change
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--Documentation/releases/coreboot-4.14-relnotes.md24
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index b6c927ee12..3593bdcc78 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -76,4 +76,28 @@ now passed from within SMM_MODULE_LOADER. Allocation and initialisations
for common ACPI GNVS table entries were largely moved to one centralized
implementation.
+### Intel Xeon Scalable Processor support is now considered mature
+
+Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed
+primarily to serve the needs of the server market.
+
+coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
+This release has support for SkyLake-SP (SKX-SP) which is the 2nd
+generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+or the latest generation [2] on market.
+
+With this release, the codebase for multiple generations of Xeon-SP
+were unified and optimized:
+* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for
+this board is in Proof Of Concept Status.
+* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for
+this board is in DVT (Design Validation Test) exit equivalent status.
+Features supported, (performance/stability) test scopes, known issues,
+features gaps are described in [4].
+
### Add significant changes here
+
+[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html
+[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html
+[3] ../mainboard/ocp/tiogapass.md
+[4] ../mainboard/ocp/deltalake.md