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authorSubrata Banik <subrata.banik@intel.com>2019-01-14 20:03:56 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-16 16:26:56 +0000
commit1ed36f9ce9d52917a04cfbe5c3b353910ca7fd1c (patch)
tree5eaa7e4a415d1af6a6c15b6dd11c0ff76a18a755
parentd4a12ec82204b9acf8dc814103e4f2efefecd248 (diff)
mainboard/intel: Update mainboard UART Kconfig
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged, all mainboard using intel cannonlake,coffeelake, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. TEST=Intel client and IoT team has verified that LPSS uart is working fine on CNL, WHL and ICL RVPs. Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30913 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/intel/cannonlake_rvp/Kconfig5
-rw-r--r--src/mainboard/intel/coffeelake_rvp/Kconfig5
-rw-r--r--src/mainboard/intel/icelake_rvp/Kconfig5
-rw-r--r--src/mainboard/intel/kblrvp/Kconfig5
4 files changed, 17 insertions, 3 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig
index 15d56c3888..d86e48564f 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_I2C_GENERIC
select SOC_INTEL_CANNONLAKE
select MAINBOARD_USES_IFD_EC_REGION
+ select INTEL_LPSS_UART_FOR_CONSOLE
config MAINBOARD_DIR
string
@@ -65,4 +66,8 @@ config DIMM_SPD_SIZE
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA
+
+config UART_FOR_CONSOLE
+ int
+ default 2
endif
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 95eeeff284..db36474bdd 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
- select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_INTEL_WHISKEYLAKE_RVP
+ select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
select DRIVERS_I2C_HID
@@ -51,8 +51,7 @@ config MAX_CPUS
config UART_FOR_CONSOLE
int
- default 2 if BOARD_INTEL_WHISKEYLAKE_RVP
- default 0
+ default 2
config DEVICETREE
string
diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig
index da9c077b6d..7cc4e535b8 100644
--- a/src/mainboard/intel/icelake_rvp/Kconfig
+++ b/src/mainboard/intel/icelake_rvp/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_ICELAKE
select MAINBOARD_USES_IFD_EC_REGION
+ select INTEL_LPSS_UART_FOR_CONSOLE
config MAINBOARD_DIR
string
@@ -51,4 +52,8 @@ config DIMM_SPD_SIZE
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA
+
+config UART_FOR_CONSOLE
+ int
+ default 2
endif
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index c3a0400b59..3795cce9f1 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM
+ select INTEL_LPSS_UART_FOR_CONSOLE
config VBOOT
select VBOOT_LID_SWITCH
@@ -84,4 +85,8 @@ config PRERAM_CBMEM_CONSOLE_SIZE
config DIMM_SPD_SIZE
int
default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4
+
+config UART_FOR_CONSOLE
+ int
+ default 2
endif