diff options
| author | Wei Hualin <weihualin@huaqin.corp-partner.google.com> | 2024-08-15 17:41:51 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-08-23 17:51:59 +0000 |
| commit | 1d41e3d1e090e26dda58dfdc0c5b5fc54e8931d8 (patch) | |
| tree | 4724faccca8fcfabcca649a16f05ac679829d6b2 | |
| parent | 62d69eb59b818fbb225fc47adababa8642bc69a1 (diff) | |
mb/google/dedede/var/awasuki: Modify DPTF parameters
Modify DPTF parameters from thermal team.
1. Add TCHG.
2. Modify the charging limit.
BUG=b:360066326
TEST=Modify Thermal according to design requirements
Change-Id: Ia7050b552656a70da0c992e4f54b02ccb6a7c114
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83929
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar
| -rw-r--r-- | src/mainboard/google/dedede/variants/awasuki/overridetree.cb | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index 2b153d0cc1..ad28296116 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -55,18 +55,18 @@ chip soc/intel/jasperlake # Power limit config register "power_limits_config[JSL_N4500_6W_CORE]" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 20, + .tdp_pl1_override = 5, + .tdp_pl2_override = 15, }" register "power_limits_config[JSL_N6000_6W_CORE]" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 20, + .tdp_pl1_override = 5, + .tdp_pl2_override = 15, }" register "power_limits_config[JSL_N5100_6W_CORE]" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 20, + .tdp_pl1_override = 5, + .tdp_pl2_override = 15, }" # TCC activation offset @@ -91,7 +91,7 @@ chip soc/intel/jasperlake ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 50, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000), + [1] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 68, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 68, 5000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 68, 5000), }" @@ -107,15 +107,15 @@ chip soc/intel/jasperlake register "controls.power_limits.pl1" = "{ .min_power = 5000, - .max_power = 7000, + .max_power = 9000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, .granularity = 125, }" register "controls.power_limits.pl2" = "{ - .min_power = 20000, - .max_power = 20000, + .min_power = 15000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, @@ -125,9 +125,8 @@ chip soc/intel/jasperlake register "controls.charger_perf" = "{ [0] = { 255, 3000 }, [1] = { 32, 2000 }, - [2] = { 24, 1500 }, - [3] = { 16, 1000 }, - [4] = { 8, 500 } + [2] = { 16, 1000 }, + [3] = { 8, 500 } }" device generic 0 on end end |