diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-02-26 19:21:39 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-28 00:36:55 +0100 |
| commit | 1cca340942957009ad74e24ef04bdd5eb44aabaf (patch) | |
| tree | 95dcf8332149483f6f77eab85c0fade9288e96b7 | |
| parent | 8f4647a24bf19a96531af9905b23ae8a2fc2675a (diff) | |
Use defines for some i82801ex/gx registers
Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex.h | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/lpc.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 2 |
4 files changed, 12 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd57e..3c7321a9fa 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -12,4 +12,11 @@ extern void i82801ex_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4) + #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360ce07..d0d597871f 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,8 +12,6 @@ #include <arch/ioapic.h> #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 #define NMI_OFF 0 #define MAINBOARD_POWER_OFF 0 @@ -193,7 +191,7 @@ static void i82801ex_gpio_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); + res = find_resource(dev, GPIO_BASE); if (!res) { return; } @@ -295,10 +293,10 @@ static void i82801ex_lpc_read_resources(device_t dev) pci_dev_read_resources(dev); /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); + res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); + res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 566311f55f..6561399389 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -80,6 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c6b76d337a..45d5c12002 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -49,7 +49,7 @@ static void i82801gx_enable_apic(struct device *dev) /* Enable ACPI I/O and power management. * Set SCI IRQ to IRQ9 */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; *ioapic_data = (1 << 25); |