diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-06-13 17:19:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-14 16:35:22 +0000 |
| commit | 1acb133e2d76a285f42198f0daba0f3ab16dc82c (patch) | |
| tree | 661fbc0d2f7f0d5a7b805ae81c7a9ca27465f9f8 | |
| parent | 68305aa3b0fb5e8b3213baa99d48238e57bad2ad (diff) | |
mb/amd/chausie/devicetree: add PCIe clock output configuration
The general purpose PCIe clock outputs 0, 1 and 3 are used with their
corresponding clock request pins, so set the gpp_clk_config to
GPP_CLK_REQ for those and disable the unused output 2. This matches the
DXIO descriptor in port_descriptors.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/amd/chausie/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index b7e0aa1a48..c0806a5c07 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -149,6 +149,11 @@ chip soc/amd/sabrina .PhyP3CpmP4Support = 0, }" + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + device domain 0 on device ref iommu on end device ref gpp_bridge_0 on end # GBE |