diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 20:01:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-03-01 19:39:05 +0000 |
| commit | 19af7bc822ada5a60ffbbd5fe233434cbbf9ae09 (patch) | |
| tree | e6a2d9f82cb98fa6435f2fd21f20c3e41bd6d4dd | |
| parent | 8a269deee6617d488b1cd4a9c51af0949cb79eca (diff) | |
soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition
According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.
Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index 00aae2cbe8..bd86aca20a 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -17,7 +17,11 @@ #define TCO_INTRD_SEL_SMI (1 << 2) #define TCO_INTRD_SEL_INT (1 << 1) -/* SMBus I/O bits. */ -#define SMBUS_SLAVE_ADDR 0x24 +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 #endif |