diff options
| author | Deepti Deshatty <deepti.deshatty@intel.com> | 2021-04-29 21:32:58 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-14 05:55:30 +0000 |
| commit | 193203f90b49de06e4997aad53fb6d556c34798f (patch) | |
| tree | 354bee59790a12266bbeee14f944369d34cc4b78 | |
| parent | b035f589401b0060771be432851c339843fffeca (diff) | |
mb/intel/adlrvp: Add board id for MR DDR5 SKU
Add support for Maple Ridge DDR5 SKU with boardid 0x16
TEST=Verified build for ADL-P Chrome RVP
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
| -rw-r--r-- | src/mainboard/intel/adlrvp/include/baseboard/variants.h | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/mainboard.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 3 |
4 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index af641488c9..9a94db2c7a 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -13,7 +13,8 @@ enum adl_boardid { ADL_P_LP4_1 = 0x10, ADL_P_LP4_2 = 0x11, /* ADL-P DDR5 RVPs */ - ADL_P_DDR5 = 0x12, + ADL_P_DDR5_1 = 0x12, + ADL_P_DDR5_2 = 0x16, /* ADL-P LPDDR5 RVP */ ADL_P_LP5_1 = 0x13, ADL_P_LP5_2 = 0x17, diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index 0ab80d2313..eb86773ca0 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -47,7 +47,8 @@ const char *mainboard_vbt_filename(void) case ADL_P_LP5_1: case ADL_P_LP5_2: return "vbt_adlrvp_lp5.bin"; - case ADL_P_DDR5: + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: return "vbt_adlrvp_ddr5.bin"; default: return "vbt.bin"; diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 29eb74497d..353cf4eff8 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -300,7 +300,8 @@ const struct mb_cfg *variant_memory_params(void) case ADL_P_DDR4_1: case ADL_P_DDR4_2: return &ddr4_mem_config; - case ADL_P_DDR5: + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: return &ddr5_mem_config; case ADL_P_LP5_1: case ADL_P_LP5_2: diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 2c611250a5..9fff25723e 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -52,7 +52,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - case ADL_P_DDR5: + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated); break; case ADL_P_LP4_1: |