diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-07-16 13:30:48 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-18 06:01:44 +0000 |
| commit | 15cfc5df3a7f36c65fa418ff3c867246900eb267 (patch) | |
| tree | 8a67f910a3f8b5be1cd5ef1eef4085a9c9b10988 | |
| parent | 825092a621af7b80d6289dd2d28ee03591e9e314 (diff) | |
soc/intel/tigerlake: Switch to common eSPI header
This patch updates Tiger Lake code to use the common eSPI header file
(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/volteer.
Change-Id: I01eca0ab132b1788c4633d0e214d4dfde25f5b98
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83488
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/espi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/espi.h | 33 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pmutil.c | 2 |
4 files changed, 3 insertions, 36 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index fc06873259..64e8b2e64c 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -18,9 +18,9 @@ #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <intelpch/espi.h> #include <soc/bootblock.h> #include <soc/soc_chip.h> -#include <soc/espi.h> #include <soc/iomap.h> #include <soc/p2sb.h> #include <soc/pch.h> diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 99bc6201da..6ef7c6d92d 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -14,7 +14,7 @@ #include <arch/ioapic.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> -#include <soc/espi.h> +#include <intelpch/espi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h deleted file mode 100644 index f9f8593996..0000000000 --- a/src/soc/intel/tigerlake/include/soc/espi.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 2 - */ - -#ifndef _SOC_TIGERLAKE_ESPI_H_ -#define _SOC_TIGERLAKE_ESPI_H_ - -/* PCI Configuration Space (D31:F0): ESPI */ -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 -#define SERIRQ_CNTL 0x64 -#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ -#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ -#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ -#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ -#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ -#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ -#define LGMR 0x98 /* ESPI Generic Memory Range */ -#define PCCTL 0xE0 /* PCI Clock Control */ -#define CLKRUN_EN (1 << 0) - -#endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index f8a7b19a8b..ba33e4984a 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -22,7 +22,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <soc/espi.h> +#include <intelpch/espi.h> #include <soc/gpe.h> #include <soc/iomap.h> #include <soc/pci_devs.h> |