diff options
| author | Martin Roth <martinroth@google.com> | 2015-10-26 10:07:24 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-28 19:22:04 +0100 |
| commit | 158d00148f77569fc4a49176bcfeb4e0f990a1ff (patch) | |
| tree | 8fc573d91f817c286aceab6a2a1bc00c3ef35037 | |
| parent | 64d04806f9fcb3c740165153d53778a95f87eed1 (diff) | |
cpu/intel/fsp_model_206ax: Load microcode in coreboot
Intel's FSP 1.0 platforms are moving back to loading microcode in
coreboot instead of in the FSP. Update the Ivy Bridge chips to
be compatible.
Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 7 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/bootblock.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 3 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 606000e4be..a1b3d71a8f 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,7 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER @@ -54,9 +54,4 @@ config ENABLE_VMX bool "Enable VMX for virtualization" default n -config CPU_MICROCODE_CBFS_LOC - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xfff70000 - endif diff --git a/src/cpu/intel/fsp_model_206ax/bootblock.c b/src/cpu/intel/fsp_model_206ax/bootblock.c index 28cbd7ef77..5543347d53 100644 --- a/src/cpu/intel/fsp_model_206ax/bootblock.c +++ b/src/cpu/intel/fsp_model_206ax/bootblock.c @@ -24,8 +24,10 @@ #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" static void bootblock_cpu_init(void) { + intel_update_microcode_from_cbfs(); } diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index 9b76c22aa2..cfe75b4ef3 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -27,6 +27,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> @@ -374,6 +375,8 @@ static void model_206ax_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); + intel_update_microcode_from_cbfs(); + /* Clear out pending MCEs */ configure_mca(); |