diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-07-15 16:02:39 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-21 16:24:00 +0000 |
| commit | 0f306e8883d5977678c8e0dc5dc183dbcebbaf74 (patch) | |
| tree | 5d8a848652b2897882b6a98cbc54bf914659e11b | |
| parent | 1412ffab198ae101e76c0d2bf4da808660027228 (diff) | |
mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR.
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
3 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc b/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc index 4f31da907d..12f2bf259d 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc @@ -2,5 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = H9HCNNNCPMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt index 8a6d608ba0..243fc55b2f 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt @@ -2,3 +2,5 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) H9HCNNNCPMMLXR-NEE 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 2 (0010) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/brya/variants/gimble/memory/mem_list_variant.txt b/src/mainboard/google/brya/variants/gimble/memory/mem_list_variant.txt index 5fd11c6485..bec9cc804a 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/mem_list_variant.txt +++ b/src/mainboard/google/brya/variants/gimble/memory/mem_list_variant.txt @@ -1,3 +1,5 @@ MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4U6E3S4AA-MGCR |