diff options
| author | Morris Hsu <morris-hsu@quanta.corp-partner.google.com> | 2023-11-30 13:56:26 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-01 15:19:08 +0000 |
| commit | 0cf76cfabeefe67302edc814effb75a6e01a5b1a (patch) | |
| tree | fbfe768f08dc4e1f6277db0617b7f65fadc4f1f8 | |
| parent | 4bd12361dcf1f31b51097943d400143168befa11 (diff) | |
mb/google/brya/var/dochi: Update overridetree for type c1
Update overridetree to correct AUX pin to USB-C port 3
BUG=b:299570339
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/dochi/overridetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index cc74f8d998..19ace7b197 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -18,14 +18,14 @@ chip soc/intel/alderlake # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. - # Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2. - # TcssAuxOri = 0101b - # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0" - # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # Bits (0,1) allocated for TCSS Port1 configuration, Bits (4,5)for TCSS Port3. + # TcssAuxOri = 010001b + # Bit0,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0" + # Bit1,Bit5 set to "0" indicates Aux lines are not swapped on the # motherboard to USBC connector - register "tcss_aux_ori" = "0x5" + register "tcss_aux_ori" = "0x11" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3 |