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authorJeremy Compostella <jeremy.compostella@intel.com>2024-02-21 12:52:43 -0800
committerMartin L Roth <gaumless@gmail.com>2024-03-09 23:47:56 +0000
commit0c74b7c1670ed3511b34c085557ac74f4752f5d5 (patch)
treeb721c499bdf0a76628bfdd60f9e50b100f02a4bd
parent5d0fa0de70145de85dcc6bd7c1ba0db19b864b89 (diff)
drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI Init
FSP can also make use of Multi-Processor services during its multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot take MP ownership as FSP-S may still use EDK2 MP services concurrently. TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/drivers/intel/fsp2_0/silicon_init.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 4da50982f2..ab51571903 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -151,7 +151,7 @@ static void do_silicon_init(struct fsp_header *hdr)
fsps_return_value_handler(FSP_SILICON_INIT_API, status);
/* Reinitialize CPUs if FSP-S has done MP Init */
- if (CONFIG(USE_INTEL_FSP_MP_INIT))
+ if (CONFIG(USE_INTEL_FSP_MP_INIT) && !fsp_is_multi_phase_init_enabled())
do_mpinit_after_fsp();
if (!CONFIG(PLATFORM_USES_FSP2_2))
@@ -197,6 +197,10 @@ static void do_silicon_init(struct fsp_header *hdr)
}
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
+
+ /* Reinitialize CPUs if FSP-S has done MP Init */
+ if (CONFIG(USE_INTEL_FSP_MP_INIT))
+ do_mpinit_after_fsp();
}
static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused)