diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 12:54:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:00:10 +0000 |
| commit | 0b39379c9c85d693b74ae7e954298bc4760285f3 (patch) | |
| tree | 5ae80b57b8c2f3a6ae8a2f85dce996170cc52f8c | |
| parent | ae5ab1826ac404aedf807ff71b769334b89e92f2 (diff) | |
sb/intel/lynxpoint: Replace HPET_ADDR
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead.
Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index fa3c523a27..7b4182e65e 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -56,7 +56,7 @@ void mainboard_romstage_entry(void) .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, + .hpet_address = CONFIG_HPET_ADDRESS, .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9c6a668214..000d159e27 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -63,8 +63,6 @@ #define DEFAULT_GPIOSIZE 0x80 #endif -#define HPET_ADDR 0xfed00000 - #include <southbridge/intel/common/rcba.h> #ifndef __ACPI__ |