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authorTristan Corrick <tristan@corrick.kiwi>2018-11-30 22:53:01 +1300
committerPatrick Georgi <pgeorgi@google.com>2018-12-03 13:08:59 +0000
commit09fc6342d27bef78aa10e03a5e27bb6322732c66 (patch)
tree3fed2109d0bfd61e905b8320434006c17662793b
parentf39e0f9318c44dc51f7b439c84bfe2fbe9940960 (diff)
sb/intel/lynxpoint: Make the finalise handler common
The ASRock H81M-HDS doesn't implement a finalise handler. To fix this, and reduce code duplication in the process, make a common implementation. There should be no functional change to boards with existing finalise handlers, since the code is identical among them and the new, common implementation. Tested on an ASRock H81M-HDS. The finalise handler works. Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/mainboard/google/beltino/smihandler.c23
-rw-r--r--src/mainboard/google/slippy/smihandler.c15
-rw-r--r--src/mainboard/intel/baskingridge/mainboard_smi.c22
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c15
4 files changed, 15 insertions, 60 deletions
diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c
index 3d9324d3be..074a3e9153 100644
--- a/src/mainboard/google/beltino/smihandler.c
+++ b/src/mainboard/google/beltino/smihandler.c
@@ -27,29 +27,6 @@
#include <superio/ite/it8772f/it8772f.h>
#include "onboard.h"
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
- intel_cpu_haswell_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- default:
- break;
- }
- return 0;
-}
-
void mainboard_smi_sleep(u8 slp_typ)
{
switch (slp_typ) {
diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c
index 3480147ec1..bab764a714 100644
--- a/src/mainboard/google/slippy/smihandler.c
+++ b/src/mainboard/google/slippy/smihandler.c
@@ -119,24 +119,9 @@ void mainboard_smi_sleep(u8 slp_typ)
while (google_chromeec_get_event() != 0);
}
-
-static int mainboard_finalized = 0;
-
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
- case APM_CNT_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
- intel_cpu_haswell_finalize_smm();
-
- mainboard_finalized = 1;
- break;
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c
index 229085d161..0fd0639b56 100644
--- a/src/mainboard/intel/baskingridge/mainboard_smi.c
+++ b/src/mainboard/intel/baskingridge/mainboard_smi.c
@@ -46,25 +46,3 @@ void mainboard_smi_sleep(u8 slp_typ)
break;
}
}
-
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
- intel_cpu_haswell_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- }
- return 0;
-}
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 87848c23c7..12e5ea2eb6 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -25,6 +25,8 @@
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <cpu/intel/haswell/haswell.h>
#include "pch.h"
#include "nvs.h"
@@ -270,11 +272,24 @@ static void southbridge_smi_apmc(void)
{
u8 reg8;
em64t101_smm_state_save_area_t *state;
+ static int chipset_finalized = 0;
/* Emulate B2 register as the FADT / Linux expects it */
reg8 = inb(APM_CNT);
switch (reg8) {
+ case APM_CNT_FINALIZE:
+ if (chipset_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return;
+ }
+
+ intel_pch_finalize_smm();
+ intel_northbridge_haswell_finalize_smm();
+ intel_cpu_haswell_finalize_smm();
+
+ chipset_finalized = 1;
+ break;
case APM_CNT_CST_CONTROL:
/* Calling this function seems to cause
* some kind of race condition in Linux