diff options
| author | Mathew King <mathewk@chromium.org> | 2021-03-12 14:01:22 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-14 19:11:42 +0000 |
| commit | 095bdecab3ea0e238071ce01b3ce0fcf4ccb2d9c (patch) | |
| tree | d53ec0aad354ee0787c8d71755d60b0e01c596e6 | |
| parent | 0671d73690397952701c9fef106a2e7b01f6f2f8 (diff) | |
mb/google/guybrush: Enable PCIe devices in devicetree
BUG=b:181690884
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index eeae88eee2..fa15509f44 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -39,6 +39,11 @@ chip soc/amd/cezanne }" device domain 0 on + device ref gpp_bridge_0 on end # WLAN + device ref gpp_bridge_1 on end # SD + device ref gpp_bridge_2 on end # WWAN + device ref gpp_bridge_3 on end # NVMe + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref xhci_0 on # USB 3.1 (USB0) |