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authorRonald G. Minnich <rminnich@gmail.com>2006-09-18 04:23:23 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-09-18 04:23:23 +0000
commit0740c31cff42e97ab16353d38a58b4bffdbb124d (patch)
tree54f86bf4ed8cca573780c3a19cca81d7e2f669df
parent50f84bdea8648d8890e2f3be09f81514094d64f8 (diff)
A fix for hynix dram problems seen at 366/244
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/northbridge/amd/gx2/raminit.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index fcc05e92f4..e45d696e35 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -85,6 +85,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* load RDSYNC */
msr = rdmsr(0x2000001f);
msr.hi = 0x000ff310;
+ /* the above setting is supposed to be good for "slow" ram. We have found that for
+ * some dram, at some clock rates, e.g. hynix at 366/244, this will actually
+ * cause errors. The fix is to just set it to 0x310. Tested on 3 boards
+ * with 3 different type of dram -- Hynix, PSC, infineon.
+ * I am leaving this comment here so that at some future time nobody is tempted
+ * to mess with this setting -- RGM, 9/2006
+ */
+ msr.hi = 0x00000310;
msr.lo = 0x00000000;
wrmsr(0x2000001f, msr);